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DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 DP83849IF phyter ? dual industrial temperature with fiber support (fx) and flexible port switching dual port 10/100 mb/s ethernet physical layer tranceiver check for samples: DP83849IF 1 introduction ? ieee 802.3u mii 1.1 features ? ieee 802.3u auto-negotiation and parallel 123 ? low-power 3.3v, 0.18 m cmos technology detection ? low power consumption < 600mw typical ? ieee 802.3u endec, 10base-t transceivers ? 3.3v mac interface and filters ? auto-mdix for 10/100 mb/s ? ieee 802.3u pcs, 100base-tx transceivers ? energy detection mode and filters ? flexible mii port assignment ? ieee 802.3u 100base-fx fiber interface ? dynamic integrity utility ? ieee 1149.1 jtag ? dynamic link quality monitoring ? integrated ansi x3.263 compliant tp-pmd physical sub-layer with adaptive equalization ? tdr based cable diagnostic and cable length and baseline wander compensation detection ? programmable led support for link, 10 /100 ? optimized latency for real time ethernet mb/s mode, activity, duplex and collision operation detect ? reference clock out ? single register access for complete phy ? rmii rev. 1.2 interface (configurable) status ? sni interface (configurable) ? 10/100 mb/s packet bist (built in self test) ? mii serial management interface (mdc and ? 80-pin tqfp package (12mm x 12mm) mdio) 1.2 applications ? medical instrumentation ? factory automation ? motor & motion control ? wireless remote base station ? general embedded applications 1.3 description the number of applications requiring ethernet connectivity continues to expand. along with this increased market demand is a change in application requirements. where single channel ethernet used to be sufficient, many applications such as wireless remote base stations and industrial networking now require dual port functionality for redundancy or system management. the DP83849IF is a highly reliable, feature rich device perfectly suited for industrial applications enabling ethernet on the factory floor. the DP83849IF features two fully independent 10/100 ports for multi-port applications. texas instruments ? unique port switching capability also allows the two ports to be configured to provide fully integrated range extension, media conversion, hardware based failover and port monitoring. the DP83849IF provides optimum flexibility in mpu selection by supporting both mii and rmii interfaces. the device also provides flexibility by supporting both copper and fiber media. in addition this device includes a powerful new diagnostics tool to ensure initial network operation and maintenance. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 phyter is a trademark of texas instruments. 3 all other trademarks are the property of their respective owners. production data information is current as of publication date. products conform to copyright ? 2008 ? 2009, texas instruments incorporated specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 1.4 description continued in addition to the tdr scheme, commonly used for detecting faults during installation, ti ? s innovative cable diagnostics provides for real time continuous monitoring of the link quality. this allows the system designer to implement a fault prediction mechanism to detect and warn of changing or deteriorating link conditions. with the DP83849IF, ti continues to build on its ethernet expertise and leadership position by providing a powerful combination of features and flexibility, easing ethernet implementation for the system designer. 2 introduction copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 1 introduction .............................................. 1 timing .............................................. 27 3.29 ac specifications ? 10 mb/s internal loopback 1.1 features .......................................... 1 timing .............................................. 28 1.2 applications ..................................... 1 3.30 ac specifications ? rmii transmit timing ........ 28 1.3 description ...................................... 1 3.31 ac specifications ? rmii receive timing ........ 29 1.4 description continued ....................... 2 3.32 ac specifications ? single clock mii (scmii) 2 device information ...................................... 5 transmit timing .................................... 30 2.1 system diagram ..................................... 5 3.33 ac specifications ? single clock mii (scmii) 2.2 block diagram ....................................... 5 receive timing ..................................... 30 2.3 connection diagram ................................. 6 3.34 ac specifications ? isolation timing .............. 31 2.4 pin descriptions ...................................... 7 3.35 ac specifications ? clk2mac timing ............ 31 3 electrical specifications ............................. 15 3.36 ac specifications ? 100 mb/s x1 to tx_clk timing .............................................. 31 3.1 absolute maximum ratings ........................ 15 4 configuration ........................................... 32 3.2 recommended operating conditions .............. 15 4.1 media configuration ......................... 32 3.3 ac and dc specifications .......................... 15 4.2 auto-negotiation .............................. 32 3.4 dc specifications .................................. 15 4.3 auto-mdix ........................................ 35 3.5 ac specifications ? power up timing ............ 17 4.4 phy address .................................... 35 3.6 ac specifications ? reset timing ................. 18 4.5 led interface ................................... 36 3.7 ac specifications ? mii serial management timing ...................................................... 19 4.6 half duplex vs. full duplex ................ 38 3.8 ac specifications ? 100 mb/s mii transmit timing 4.7 internal loopback ............................ 38 ...................................................... 19 4.8 bist ................................................ 38 3.9 ac specifications ? 100 mb/s mii receive timing 19 5 mac interface .......................................... 40 3.10 ac specifications ? 100base-tx and 100base- 5.1 mii interface .................................... 40 fx mii transmit packet latency timing ........... 20 5.2 reduced mii interface ....................... 41 3.11 ac specifications ? 100base-tx and 100base- fx mii transmit packet deassertion timing ....... 20 5.3 10 mb serial network interface (sni) .... 42 3.12 ac specifications ? 100base-tx transmit timing 5.4 single clock mii mode ........................ 42 (t r/f & jitter) ........................................ 21 5.5 flexible mii port assignment .............. 43 3.13 ac specifications ? 100base-tx and 100base- 5.6 802.3u mii serial management interface . 46 fx mii receive packet latency timing ............ 21 6 architecture ............................................. 49 3.14 ac specifications ? 100base-tx and 100base- 6.1 100base-tx transmitter ...................... 49 fx mii receive packet deassertion timing ....... 22 6.2 100base-tx receiver .......................... 51 3.15 ac specifications ? 10 mb/s mii transmit timing 22 6.3 100base-fx operation ......................... 56 3.16 ac specifications ? 10 mb/s mii receive timing . 22 6.4 10base-t transceiver module .............. 56 3.17 ac specifications ? 10 mb/s serial mode transmit timing .............................................. 23 7 design guidelines ..................................... 60 3.18 ac specifications ? 10 mb/s serial mode receive 7.1 tpi network circuit .......................... 60 timing .............................................. 23 7.2 fiber network circuit ....................... 61 3.19 ac specifications ? 10base-t transmit timing 7.3 esd protection ................................ 61 (start of packet) ................................... 23 7.4 clock in (x1) requirements ................. 62 3.20 ac specifications ? 10base-t transmit timing 7.5 power feedback circuit .................... 63 (end of packet) ..................................... 24 3.21 ac specifications ? 10base-t receive timing 7.6 power down/interrupt ...................... 63 (start of packet) .................................... 24 7.7 energy detect mode ......................... 64 3.22 ac specifications ? 10base-t receive timing 7.8 link diagnostic capabilities ................ 64 (end of packet) ..................................... 25 8 reset operation ........................................ 69 3.23 ac specifications ? 10 mb/s heartbeat timing ... 25 8.1 hardware reset ............................... 69 3.24 ac specifications ? 10 mb/s jabber timing ...... 25 8.2 full software reset ......................... 69 3.25 ac specifications ? 10base-t normal link pulse 8.3 soft reset ...................................... 69 timing .............................................. 26 9 register block ......................................... 70 3.26 ac specifications ? auto-negotiation fast link pulse (flp) timing ................................. 26 9.1 register definition ........................... 73 3.27 ac specifications ? 100base-tx signal detect 9.2 extended registers - page 0 ............... 84 timing .............................................. 26 9.3 link diagnostics registers - page 2 ...... 93 3.28 ac specifications ? 100 mb/s internal loopback copyright ? 2008 ? 2009, texas instruments incorporated contents 3 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 4 contents copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 2 device information 2.1 system diagram 2.2 block diagram figure 2-1. DP83849IF functional block diagarm copyright ? 2008 ? 2009, texas instruments incorporated device information 5 submit documentation feedback product folder links: DP83849IF leds leds jtag tprd/fxrd+ tptd/fxtd+ led drivers led drivers mdc mdio tx rx rx tx management interface boundary scan port b port a 10/100 phy core 10/100 phy core mii management interface port b mii/rmii/sni port a mii/rmii/sni tprd/fxrd+ tptd/fxtd+ 100base-tx 100base-tx port a port b status leds 25 mhz clock source mac mac m ii/r ii/s n i m m ii/r ii/s n i m dp838491f typical application m p u / c p u 10base-fx 10base-fx rj 45 rj 45 magnetics magnetics 10base-t or 10base-t or
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 2.3 connection diagram figure 2-2. top view package number pfc 6 device information copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 2.4 pin descriptions the DP83849IF pins are classified into the following interface categories (each interface is described in the sections that follow): ? serial management interface ? mac data interface ? clock interface ? led interface ? jtag interface ? reset and power down ? strap options ? 10/100 mb/s pmd interface ? special connect pins ? power and ground pins note strapping pin option. please see section 2.4.2 for strap definitions. all DP83849IF signal pins are i/o cells regardless of the particular use. the definitions below define the functionality of the i/o cells for each pin. type: i input type: o output type: i/o input/output type od open drain type: pd,pu internal pulldown/pullup type: s strapping pin (all strap pins have weak internal pull-ups or pull-downs. if the default strap value is to be changed then an external 2.2 k ? resistor should be used. please see section 2.4.2 for details.) table 2-1. serial management interface signal name type pin # description mdc i 67 management data clock: synchronous clock to the mdio management data input/output serial interface which may be asynchronous to transmit and receive clocks. the maximum clock rate is 25 mhz with no minimum clock rate. mdio i/o 66 management data i/o: bi-directional management instruction/data signal that may be sourced by the station management entity or the phy. this pin requires a 1.5 k ? pullup resistor. copyright ? 2008 ? 2009, texas instruments incorporated device information 7 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com table 2-2. mac data interface signal name type pin # description tx_clk_a o 12 mii transmit clock: 25 mhz transmit clock output in 100 mb/s mode or 2.5 mhz in 10 mb/s tx_clk_b 50 mode derived from the 25 mhz reference clock. unused in rmii mode. the device uses the x1 reference clock input as the 50 mhz reference for both transmit and receive. sni transmit clock: 10 mhz transmit clock output in 10 mb sni mode. the mac should source tx_en and txd_0 using this clock. tx_en_a i 13 mii transmit enable: active high input indicates the presence of valid data inputs on tx_en_b 49 txd[3:0]. rmii transmit enable: active high input indicates the presence of valid data on txd[1:0]. sni transmit enable: active high input indicates the presence of valid data on txd_0. txd[3:0]_a i 17,16,15,14, mii transmit data: transmit data mii input pins, txd[3:0], that accept data synchronous to txd[3:0]_b 45,46,47,48 the tx_clk (2.5 mhz in 10 mb/s mode or 25 mhz in 100 mb/s mode). rmii transmit data: transmit data rmii input pins, txd[1:0], that accept data synchronous to the 50 mhz reference clock. sni transmit data: transmit data sni input pin, txd_0, that accept data synchronous to the tx_clk (10 mhz in 10 mb/s sni mode). rx_clk_a o 79 mii receive clock: provides the 25 mhz recovered receive clocks for 100 mb/s mode and 2.5 rx_clk_b 63 mhz for 10 mb/s mode. unused in rmii mode. the device uses the x1 reference clock input as the 50 mhz reference for both transmit and receive. sni receive clock: provides the 10 mhz recovered receive clocks for 10 mb/s sni mode. rx_dv_a o 80 mii receive data valid: asserted high to indicate that valid data is present on the rx_dv_b 62 corresponding rxd[3:0]. rmii receive data valid: asserted high to indicate that valid data is present on the corresponding rxd[1:0]. this signal is not required in rmii mode, since crs_dv includes the rx_dv signal, but is provided to allow simpler recovery of the receive data. this pin is not used in sni mode. rx_er_a o 2 mii receive error: asserted high synchronously to rx_clk to indicate that an invalid symbol rx_er_b 60 has been detected within a received packet in 100 mb/s mode. rmii receive error: asserted high synchronously to x1 whenever an invalid symbol is detected, and crs_dv is asserted in 100 mb/s mode. this pin is also asserted on detection of a false carrier event. this pin is not required to be used by a mac in rmii mode, since the phy is required to corrupt data on a receive error. this pin is not used in sni mode. rxd[3:0]_a o 9,8,5,4,53, mii receive data: nibble wide receive data signals driven synchronously to the rx_clk, 25 rxd[3:0]_b 56,57,58 mhz for 100 mb/s mode, 2.5 mhz for 10 mb/s mode). rxd[3:0] signals contain valid data when rx_dv is asserted. rmii receive data: 2-bits receive data signals, rxd[1:0], driven synchronously to the x1 clock, 50 mhz. sni receive data: receive data signal, rxd_0, driven synchronously to the rx_clk. rxd_0 contains valid data when crs is asserted. rxd[3:1] are not used in this mode. crs_a/crs_ o 1 mii carrier sense: asserted high to indicate the receive medium is non-idle. dv_a 61 rmii carrier sense/receive data valid : this signal combines the rmii carrier and crs_b/crs_ receive data valid indications. for a detailed description of this signal, see the rmii specification. dv_b sni carrier sense: asserted high to indicate the receive medium is non-idle. it is used to frame valid receive data on the rxd_0 signal. col_a o 3 mii collision detect: asserted high to indicate detection of a collision condition col_b 59 (simultaneous transmit and receive activity) in 10 mb/s and 100 mb/s half duplex modes. while in 10base-t half duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1 s at the end of transmission to indicate heartbeat (sqe test). in full duplex mode, for 10 mb/s or 100 mb/s operation, this signal is always logic 0. there is no heartbeat function during 10 mb/s full duplex operation. rmii collision detect: per the rmii specification, no col signal is required. the mac will recover crs from the crs_dv signal and use that along with its tx_en signal to determine collision. sni collision detect: asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 mb/s sni mode. 8 device information copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 2-3. clock interface signal name type pin # description x1 i 70 crystal/oscillator input: this pin is the primary clock reference input for the DP83849IF and must be connected to a 25 mhz 0.005% ( 50 ppm) clock source. the DP83849IF supports either an external crystal resonator connected across pins x1 and x2, or an external cmos-level oscillator source connected to pin x1 only. rmii reference clock: this pin is the primary clock reference input for the rmii mode and must be connected to a 50 mhz 0.005% ( 50 ppm) cmos-level oscillator source. x2 o 69 crystal output: this pin is the primary clock reference output to connect to an external 25 mhz crystal resonator device. this pin must be left unconnected if an external cmos oscillator clock source is used. clk2mac o 68 clock to mac: in mii mode, this pin provides a 25 mhz clock output to the system. in rmii mode, this pin provides a 50 mhz clock output to the system. this allows other devices to use the reference clock from the DP83849IF without requiring additional clock sources. if the system does not require the clk2mac signal, the clk2mac output should be disabled via the clk2mac disable strap. 2.4.1 led interface the DP83849IF supports three configurable led pins. the leds support two operational modes which are selected by the led mode strap and a third operational mode which is register configurable. the definitions for the leds for each mode are detailed below. since the leds are also used as strap options, the polarity of the led output is dependent on whether the pin is pulled up or down. table 2-4. led interface signal name type pin # description led_link_a i/o 19 link led: in mode 1, this pin indicates the status of the link. the led will be led_link_b on when link is good. 43 link/act led: in mode 2 and mode 3, this pin indicates transmit and receive activity in addition to the status of the link. the led will be on when link is good. it will blink when the transmitter or receiver is active. led_speed_a i/o 20 speed led: the led is on when device is in 100 mb/s and off when in 10 mb/s. functionality of this led is independent of mode selected. led_speed_b 42 led_act/led_col_a i/o 21 activity led: in mode 1, this pin is the activity led which is on when activity led_act/led_col_b is present on either transmit or receive. 41 collision/duplex led: in mode 2, this pin by default indicates collision detection. for mode 3, this led output may be programmed to indicate full- duplex status instead of collision. table 2-5. jtag interface signal name type pin # description tck i, pu 72 test clock this pin has a weak internal pullup. tdo o 73 test output tms i, pu 74 test mode select this pin has a weak internal pullup. trstn i, pu 75 test reset active low test reset. this pin has a weak internal pullup. tdi i, pu 76 test data input this pin has a weak internal pullup. copyright ? 2008 ? 2009, texas instruments incorporated device information 9 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com table 2-6. reset and power down signal name type pin # description reset_n i, pu 71 reset: active low input that initializes or re-initializes the DP83849IF. asserting this pin low for at least 1 s will force a reset process to occur. all internal registers will re-initialize to their default states as specified for each bit in the register block section. all strap options are re-initialized as well. pwrdown_int_a i, pu 18 the default function of this pin is power down. pwrdown_int_b 44 power down: the pin is an active low input in this mode and should be asserted low to put the device in a power down mode. interrupt: the pin is an open drain output in this mode and will be asserted low when an interrupt condition occurs. although the pin has a weak internal pull-up, some applications may require an external pull-up resister. register access is required for the pin to be used as an interrupt mechanism. see section 7.6.2 for more details on the interrupt mechanisms. 2.4.2 strap options the DP83849IF uses many of the functional pins as strap options. the values of these pins are sampled during reset and used to strap the device into specific modes of operation. the strap option pin assignments are defined below. the functional pin name is indicated in parentheses. a 2.2 k ? resistor should be used for pull-down or pull-up to change the default strap option. if the default option is required, then there is no need for external pull-up or pull down resistors. since these pins may have alternate functions after reset is deasserted, they should not be connected directly to v cc or gnd. table 2-7. strap options signal name type pin # description phyad1 (rxd0_a) s, o, pd 4 phy address [4:1]: the DP83849IF provides four phy address pins, the state of phyad2 (rxd1_a) s, o, pd 5 which are latched into the phyctrl register at system hardware-reset. phy phyad3 (rxd0_b) s, o, pd 58 address[0] selects between ports a and b. phyad4 (rxd1_b) s, o, pd 57 the DP83849IF supports phy address strapping for port a even values 0 ( < 0000_0 > ) through 30 ( < 1111_0 > ). port b will be strapped to odd values 1 ( < 0000_1 > ) through 31 ( < 1111_1 > ). phyad[4:1] pins have weak internal pull-down resistors. 10 device information copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 2-7. strap options (continued) signal name type pin # description fx_en_a (col_a) s, i, pd 3 fx enable: default is to disable 100base-fx (fiber) mode. this strapping option fx_en_b (col_b) 59 enables 100base-fx. an external pull-up will enable 100base-fx mode. auto-negotiation enable: when high, this enables auto-negotiation with the capability an_en s, o, pu 21 set by an0 and an1 pins. when low, this puts the part into forced mode with the (led_act/led_col_a) 20 capability set by an0 and an1 pins. an1_a (led_speed_a) 19 an0 / an1: these input pins control the forced or advertised operating mode of the an0_a (led_link_a) DP83849IF according to the following table. the value on these pins is set by connecting the input pins to gnd (0) or v cc (1) through 2.2 k ? resistors. these pins an_en 41 should never be connected directly to gnd or v cc . (led_act/led_col_b) 42 fiber mode duplex selection: if fiber mode is strapped using the fx_en pin, the an0 an1_b (led_speed_b) 43 strap value is used to select half or full duplex. an_en and an1are ignored if fx_en an0_b (led_link_b) is asserted, since fiber mode is 100mb only and does not support auto-negotiation. the value set at this input is latched into the DP83849IF at hardware-reset. the float/pull-down status of these pins are latched into the basic mode control register and the auto_negotiation advertisement register during hardware-reset. the default is 0111 since the fx_en pin has an internal pull-down and the auto- negotiation pins have internal pull-ups. fx_en an_en an1 an0 forced mode 0 0 0 0 10base-t, half-duplex 0 0 0 1 10base-t, full-duplex 0 0 1 0 100base-tx, half-duplex 0 0 1 1 100base-tx, full-duplex 1 x x 0 100base-fx, half-duplex 1 x x 1 100base-fx, full-duplex fx_en an_en an1 an0 advertised mode 0 1 0 0 10base-t, half/full-duplex 0 1 0 1 100base-tx, half/full-duplex 0 1 1 0 10base-t, half-duplex, 100base-tx, half-duplex 0 1 1 1 10base-t, half/full-duplex, 100base-tx, half/full-duplex mii_mode_a (rx_dv_a) s, o, pd 80 mii mode select: this strapping option pair determines the operating mode of the sni_mode_a (txd3_a) 17 mac data interface. default operation (no pull-ups) will enable normal mii mode of mii_mode_b (rx_dv_b) 62 operation. strapping mii_mode high will cause the device to be in rmii or sni modes sni_mode_b (txd3_b) 45 of operation, determined by the status of the sni_mode strap. since the pins include internal pull-downs, the default values are 0. both mac data interfaces must have their rmii mode settings the same, i.e. both in rmii mode or both not in rmii mode. the following table details the configurations: mii_mode sni_mode mac interface mode 0 x mii mode 1 0 rmii mode 1 1 10 mb sni mode led_cfg_a s, o, pu 1 led configuration: this strapping option determines the mode of operation of the (crs_a/crs_dv_a) 61 led pins. default is mode 1. mode 1 and mode 2 can be controlled via the strap option. led_cfg_b all modes are configurable via register access. (crs_b/crs_dv_b) see table 4-3 for led mode selection. copyright ? 2008 ? 2009, texas instruments incorporated device information 11 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com table 2-7. strap options (continued) signal name type pin # description mdix_en_a (rx_er_a) s, o, pu 2 mdix enable: default is to enable mdix. this strapping option disables auto-mdix. mdix_en_b (rx_er_b) 60 an external pull-down will disable auto-mdix mode. ed_en_a (rxd3_a) s, o, pd 9 energy detect enable: default is to disable energy detect mode. this strapping ed_en_b (rxd3_b) 53 option enables energy detect mode for the port. in energy detect mode, the device will initially be in a low-power state until detecting activity on the wire. an external pull-up will enable energy detect mode. clk2mac_dis (rxd2_a) s, o, pd 8 clock to mac disable: this strapping option disables (floats) the clk2mac pin. default is to enable clk2mac output. an external pullup will disable (float) the clk2mac pin. if the system does not require the clk2mac signal, the clk2mac output should be disabled via this strap option. extender_en (rxd2_b) s, o, pd 56 extender mode enable: this strapping option enables extender mode for both ports. when enabled, the strap will enable single clock mii tx and rx modes unless rmii mode is also strapped. sni mode cannot be strapped if extender mode is strapped. table 2-8. 10 mb/s and 100 mb/s pmd interface signal name type pin # description tptdm_a/fxtdm_a i/o 26 10base-t or 100base-tx or 100base-fx transmit data tptdp_a/fxtdp_a 27 in 10base-t or 100base-tx: differential common driver transmit output tptdm_b/fxtdm_b 36 (pmd output pair). these differential outputs are automatically configured to tptdp_b/fxtdp_b 35 either 10base-t or 100base-tx signaling. in auto-mdix mode of operation, this pair can be used as the receive input pair. in 100base-fx mode, this pair becomes the 100base-fx transmit pair. these pins require 3.3v bias for operation. tprdm_a/fxrdm_a i/o 23 10base-t or 100base-tx or 100base-fx receive data tprdp_a/fxrdp_a 24 in 10base-t or 100base-tx: differential receive input (pmd input pair). tprdm_b/fxrdm_b 39 these differential inputs are automatically configured to accept either tprdp_b/fxrdp_b 38 100base-tx or 10base-t signaling. in auto-mdix mode of operation, this pair can be used as the transmit output pair. in 100base-fx mode, this pair becomes the 100base-fx receive pair. these pins require 3.3v bias for operation. fxsd_a(led_speed_a/ana) i 20 fx signal detect: this pin provides the signal detect input for 100base-fx fxsd_b(led_speed_b/an1_b) 42 mode. table 2-9. special connections signal name type pin # description rbias i 32 bias resistor connection: a 4.87 k ? 1% resistor should be connected from rbias to gnd. pfbout o 31 power feedback output: parallel caps, 10 f and 0.1 f, should be placed close to the pfbout. connect this pin to pfbin1 (pin 13), pfbin2 (pin 27), pfbin3 (pin 35), pfbin4 (pin 49). see section 7.5 for proper placement pin. pfbin1 i 7 power feedback input: these pins are fed with power from pfbout pin. a small capacitor pfbin2 28 of 0.1 f should be connected close to each pin (1) . pfbin3 34 pfbin4 54 (1) do not supply power to these pins other than from pfbout. table 2-10. power supply pins signal name pin # description iovdd1, iovdd2, iovdd3, iovdd4 11,51,65,78 i/o 3.3v supply iognd1, iognd2, iognd3, iognd4 10,52,64,77 i/o ground coregnd1, coregnd2 6,55 core ground cdgnd1, cdgnd2 25,37 cd ground ana33vdd 30 analog 3.3v supply anagnd1, anagnd2, anagnd3, anagnd4 22,29,33,40 analog ground 12 device information copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 2-11. package pin assignments pfc pin # pin name 1 crs_a/crs_dv_a/led_cfg_a 2 rx_er_a/mdix_en_a 3 col_a/fx_en_a 4 rxd0_a/phyad1 5 rxd1_a/phyad2 6 coregnd1 7 pfbin1 8 rxd2_a/clk2mac_dis 9 rxd3_a/ed_en_a 10 iognd1 11 iovdd1 12 tx_clk_a 13 tx_en_a 14 txd0_a 15 txd1_a 16 txd2_a 17 txd3_a/sni_mode_a 18 pwrdown_int_a 19 led_link_a/an0_a 20 led_speed_a/fxsd_a/an1_a 21 led_act/led_col/an_en_a 22 anagnd1 23 tprdm_a/fxrdm_a 24 tprdp_a/fxrdp_a 25 cdgnd1 26 tptdm_a/fxtdm_a 27 tptdp_a/fxtdp_a 28 pfbin2 29 anagnd2 30 ana33vdd 31 pfbout 32 rbias 33 anagnd3 34 pfbin3 35 tptdp_b/fxtdp_b 36 tptdm_b/fxtdm_b 37 cdgnd2 38 tprdp_b/fxrdp_b 39 tprdm_b/fxrdm_b 40 anagnd4 41 led_act/led_col/an_en_b 42 led_speed_b/fxsd_b/an1_b 43 led_link_b/an0_b 44 pwrdown_int_b 45 txd3_b/sni_mode_b 46 txd2_b 47 txd1_b copyright ? 2008 ? 2009, texas instruments incorporated device information 13 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com table 2-11. package pin assignments (continued) pfc pin # pin name 48 txd0_b 49 tx_en_b 50 tx_clk_b 51 iovdd2 52 iognd2 53 rxd3_b/ed_en_b 54 pfbin4 55 coregnd2 56 rxd2_b/extender_en 57 rxd1_b/phyad4 58 rxd0_b/phyad3 59 col_b/fx_en_b 60 rx_er_b/mdix_en_b 61 crs_b/crs_dv_b/led_cfg_b 62 rx_dv_b/mii_mode_b 63 rx_clk_b 64 iognd3 65 iovdd3 66 mdio 67 mdc 68 clk2mac 69 x2 70 x1 71 reset_n 72 tck 73 tdo 74 tms 75 trstn 76 tdi 77 iognd4 78 iovdd4 79 rx_clk_a 80 rx_dv_a/mii_mode_a 14 device information copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 3 electrical specifications 3.1 absolute maximum ratings (1) (2) supply voltage (v cc ) -0.5 v to 4.2 v dc input voltage (v in ) -0.5v to v cc + 0.5v dc output voltage (v out ) -0.5v to v cc + 0.5v maximum temperature for ta = 85 c 108 c maximum die temperature (tj) 150 c storage temperature (t stg ) -65 c to 150 c lead temp. (tl) (soldering, 10 sec.) 260 c esd rating (r zap = 1.5k, c zap = 100 pf) 4.0 kv (1) absolute maximum ratings are those values beyond which the safety of the device cannot be specified. they are not meant to imply that the device should be operated at these limits. (2) if military/aerospace specified devices are required, please contact the ti sales office/ distributors for availability and specifications. 3.2 recommended operating conditions supply voltage (v cc ) 3.3 volts 0.3v industrial - ambient temperature (t a ) -40 to 85 c power dissipation (p d ) 594 mw 3.3 ac and dc specifications thermal characteristic max units theta junction to case (t jc ) 17.3 c / w theta junction to ambient (t ja ) degrees celsius/watt - no airflow @ 1.0 w 53 c / w 3.4 dc specifications pin symbol parameter conditions min typ max units types v ih i input high voltage nominal v cc 2 v i/o v il i input low voltage 0.8 v i/o i ih i input high current vin = v cc 10 a i/o i il i input low current vin = gnd 10 a i/o v ol o, output low iol = 4 ma 0.4 v i/o voltage v oh o, output high ioh = -4 ma v cc - 0.5 v i/o voltage i oz i/o, tri-state vout = v cc 10 a o leakage v tptd_100 pmd output 100m transmit voltage 0.95 1 1.05 v pair v tptdsym pmd output 100m transmit voltage symmetry 2 % pair v tptd_10 pmd output 10m transmit voltage 2.2 2.5 2.8 v pair copyright ? 2008 ? 2009, texas instruments incorporated electrical specifications 15 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com dc specifications (continued) pin symbol parameter conditions min typ max units types v fxtd_100 pmd output fx100m transmit voltage 0.3 0.5 0.93 v pair c in1 i cmos input 8 pf capacitance c out1 o cmos output 8 pf capacitance s dthon pmd input 100base-tx mv diff 1000 pair pk-pk signal detect turn-on threshold s dthoff pmd input 100base-tx mv diff 200 pair pk-pk signal detect turn-off threshold v th1 pmd input 10base-t receive threshold 585 mv pair i dd100 supply 100base-tx 180 ma (full duplex) i dd10 supply 10base-t 180 ma (full duplex) i dd supply power down mode clk2mac disabled 9.5 ma 16 electrical specifications copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 3.5 ac specifications ? power up timing (1) parameter description notes min typ max units t2.1.1 post power up stabilization time mdio is pulled high for 32-bit serial 167 ms prior to mdc preamble for register management initialization accesses x1 clock must be stable for a min. of 167ms at power up. t2.1.2 hardware configuration latch-in hardware configuration pins are 167 ms time from power up described in the pin description section. x1 clock must be stable for a min. of 167ms at power up. t2.1.3 hardware configuration pins 50 ns transition to output drivers (1) in rmii mode, the minimum post power up stabilization and hardware configuration latch-in times are 84ms. copyright ? 2008 ? 2009, texas instruments incorporated electrical specifications 17 submit documentation feedback product folder links: DP83849IF t2.1.1 t2.1.2 32 clocks t2.1.3 output input vcc x1 clock hardware reset_n mdc latch-in of hardware configuration pins dual function pins become enabled as outputs
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 3.6 ac specifications ? reset timing (1) parameter description notes min typ max units t2.2.1 post reset stabilization time prior to mdio is pulled high for 32-bit serial 3 s mdc preamble for register accesses management initialization t2.2.2 hardware configuration latch-in time hardware configuration pins are 3 s from the deassertion of reset (either described in the pin description soft or hard) section t2.2.3 hardware configuration pins transition 50 ns to output drivers t2.2.4 reset pulse width x1 clock must be stable for at min. 1 s of 1us during reset pulse low time. (1) it is important to choose pull-up and/or pull-down resistors for each of the hardware configuration pins that provide fast rc time constants in order to latch-in the proper value prior to the pin transitioning to an output driver. 18 electrical specifications copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF t2.2.4 t2.2.2 32 clocks t2.2.3 output input vcc x1 clock hardware reset_n mdc latch-in of hardware configuration pins dual function pins become enabled as outputs t2.2.1
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 3.7 ac specifications ? mii serial management timing parameter description notes min typ max units t2.3.1 mdc to mdio (output) delay time 0 30 ns t2.3.2 mdio (input) to mdc setup time 10 ns t2.3.3 mdio (input) to mdc hold time 10 ns t2.3.4 mdc frequency 2.5 25 mhz 3.8 ac specifications ? 100 mb/s mii transmit timing parameter description notes min typ max units t2.4.1 tx_clk high/low time 100 mb/s normal mode 16 20 24 ns t2.4.2 txd[3:0], tx_en data setup to 100 mb/s normal mode 10 ns tx_clk t2.4.3 txd[3:0], tx_en data hold from 100 mb/s normal mode 0 ns tx_clk 3.9 ac specifications ? 100 mb/s mii receive timing (1) parameter description notes min typ max units t2.5.1 rx_clk high/low time 100 mb/s normal mode 16 20 24 ns t2.5.2 rx_clk to rxd[3:0], rx_dv, rx_er 100 mb/s normal mode 10 30 ns delay (1) rx_clk may be held low or high for a longer period of time during transition between reference and recovered clocks. minimum high and low times will not be violated. copyright ? 2008 ? 2009, texas instruments incorporated electrical specifications 19 submit documentation feedback product folder links: DP83849IF tx_cl k txd[3:0 ] valid data t2.4.2 t2.4.3 tx_en t2.4.1 t2.4.1 valid data t2.5.1 t2.5.1 t2.5.2 rx_clk rxd[3:0] rx_dv rx_er mdc mdio (output) mdc mdio (input) t2.3.4 t2.3.1 valid data t2.3.2 t2.3.3
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 3.10 ac specifications ? 100base-tx and 100base-fx mii transmit packet latency timing (1) parameter description notes min typ max units t2.6.1 tx_clk to pmd output pair latency 100base-tx and 100base-fx modes 5 bits (1) for normal mode, latency is determined by measuring the time from the first rising edge of tx_clk occurring after the assertion of tx_en to the first bit of the ? j ? code group as output from the pmd output pair. 1 bit time = 10 ns in 100 mb/s mode. 3.11 ac specifications ? 100base-tx and 100base-fx mii transmit packet deassertion timing (1) parameter description notes min typ max units t2.7.1 tx_clk to pmd output pair deassertion 100base-tx and 100base-fx modes 5 bits (1) deassertion is determined by measuring the time from the first rising edge of tx_clk occurring after the deassertion of tx_en to the first bit of the ? t ? code group as output from the pmd output pair. 1 bit time = 10 ns in 100 mb/s mode. 20 electrical specifications copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF tx_clk tx_en txd pmd output pair idle data (j/k) t2.7.1 tx_clk tx_en txd pmd output pair idle data (j/k) t2.6.1
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 3.12 ac specifications ? 100base-tx transmit timing (t r/f & jitter) (1) parameter description notes min typ max units t2.8.1 100 mb/s pmd output pair t r and t f 3 4 5 ns 100 mb/s t r and t f mismatch (2) 500 ps t2.8.2 100 mb/s pmd output pair transmit jitter 1.4 ns (1) rise and fall times taken at 10% and 90% of the +1 or -1 amplitude (2) normal mismatch is the difference between the maximum and minimum of all rise and fall times 3.13 ac specifications ? 100base-tx and 100base-fx mii receive packet latency timing (1) (2) parameter description notes min typ max units t2.9.1 carrier sense on delay (3) 100base-tx mode 20 bits 100base-fx mode 10 t2.9.2 receive data latency 100base-tx mode 24 bits 100base-fx mode 14 (1) pmd input pair voltage amplitude is greater than the signal detect turn-on threshold value. (2) 1 bit time = 10 ns in 100 mb/s mode. (3) carrier sense on delay is determined by measuring the time from the first bit of the ? j ? code group to the assertion of carrier sense. copyright ? 2008 ? 2009, texas instruments incorporated electrical specifications 21 submit documentation feedback product folder links: DP83849IF data (j/k) idle t2.9.2 t2.9.1 crs pmd input pair rxd[3:0] rx_dv rx_er 10% 90% +1 rise +1 fall -1 fall -1 rise 90% 10% t2.8.1 t2.8.1 t2.8.1 t2.8.1 pmd output pair t2.8.2 pmd output pair eye pattern t2.8.2
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 3.14 ac specifications ? 100base-tx and 100base-fx mii receive packet deassertion timing (1) parameter description notes min typ max units t2.10.1 carrier sense off delay (2) 100base-tx mode 24 bits 100base-fx mode 14 (1) 1 bit time = 10 ns in 100 mb/s mode. (2) carrier sense off delay is determined by measuring the time from the first bit of the ? t ? code group to the deassertion of carrier sense. 3.15 ac specifications ? 10 mb/s mii transmit timing (1) parameter description notes min typ max units t2.11.1 tx_clk high/low time 10 mb/s mii mode 190 200 210 ns t2.11.2 txd[3:0], tx_en data setup to 10 mb/s mii mode 25 ns tx_clk fall t2.11.3 txd[3:0], tx_en data hold from 10 mb/s mii mode 0 ns tx_clk rise (1) an attached mac should drive the transmit signals using the positive edge of tx_clk. as shown above, the mii signals are sampled on the falling edge of tx_clk. 3.16 ac specifications ? 10 mb/s mii receive timing (1) parameter description notes min typ max units t2.12.1 rx_clk high/low time 160 200 240 ns t2.12.2 rx_clk to rxd[3:0}, rx_dv delay 10 mb/s mii mode 100 ns t2.12.3 rx_clk rising edge delay from 10 mb/s mii mode 100 ns rxd[3:0], rx_dv valid (1) rx_clk may be held low for a longer period of time during transition between reference and recovered clocks. minimum high and low times will not be violated. 22 electrical specifications copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF t2.12.1 t2.12.3 t2.12.2 valid data rx_clk rxd[3:0] rx_dv t2.12.1 t2.11.1 t2.11.1 t2.11.2 t2.11.3 valid data tx_clk txd[3:0] tx_en idle (t/r) data t2.10.1 crs pmd input pair
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 3.17 ac specifications ? 10 mb/s serial mode transmit timing parameter description notes min typ max units t2.13.1 tx_clk high time 10 mb/s serial mode 20 25 30 ns t2.13.2 tx_clk low time 10 mb/s serial mode 70 75 80 ns t2.13.3 txd_0, tx_en data setup to 10 mb/s serial mode 25 ns tx_clk rise t2.13.4 txd_0, tx_en data hold from 10 mb/s serial mode 0 ns tx_clk rise 3.18 ac specifications ? 10 mb/s serial mode receive timing (1) parameter description notes min typ max units t2.14.1 rx_clk high/low time 35 50 65 ns t2.14.2 rx_clk fall to rxd_0, rx_dv delay 10 mb/s serial mode -10 10 ns (1) rx_clk may be held high for a longer period of time during transition between reference and recovered clocks. minimum high and low times will not be violated. 3.19 ac specifications ? 10base-t transmit timing (start of packet) (1) parameter description notes min typ max units t2.15.1 transmit output delay from the 10 mb/s mii mode 3.5 bits falling edge of tx_clk t2.15.2 transmit output delay from the 10 mb/s serial mode 3.5 bits rising edge of tx_clk (1) 1 bit time = 100 ns in 10mb/s. copyright ? 2008 ? 2009, texas instruments incorporated electrical specifications 23 submit documentation feedback product folder links: DP83849IF t.2.15.2 t2.15.1 tx_clk tx_en txd valid data t2.14.1 t2.14.1 t2.14.2 rx_clk rxd[0] rx_dv tx_clk valid data t2.13.3 t2.13.4 t2.13.1 t2.13.2
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 3.20 ac specifications ? 10base-t transmit timing (end of packet) parameter description notes min typ max units t2.16.1 end of packet high time 250 300 ns (with ' 0 ' ending bit) t2.16.2 end of packet high time 250 300 ns (with ' 1 ' ending bit) 3.21 ac specifications ? 10base-t receive timing (start of packet) (1) (2) parameter description notes min typ max units t2.17.1 carrier sense turn on delay (pmd 630 1000 ns input pair to crs) t2.17.2 rx_dv latency 10 bits t2.17.3 receive data latency measurement shown from sfd 8 bits (1) 10base-t rx_dv latency is measured from first bit of preamble on the wire to the assertion of rx_dv (2) 1 bit time = 100 ns in 10 mb/s mode. 24 electrical specifications copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF data sfd preamble 0000 t2.17.3 t2.17.2 t2.17.1 1 0 1 0 1 0 1 0 1 0 1 1 tprd crs rx-dv rxd[3:0] 1st sfd bit decoded tx_clk tx_en 0 0 1 1 t2.16.1 t2.16.2 pmd output pair pmd output pair
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 3.22 ac specifications ? 10base-t receive timing (end of packet) parameter description notes min typ max units t2.18.1 carrier sense turn off delay 1 s 3.23 ac specifications ? 10 mb/s heartbeat timing parameter description notes min typ max units t2.19.1 cd heartbeat delay 10 mb/s half-duplex mode 1200 ns t2.19.2 cd heartbeat duration 10 mb/s half-duplex mode 1000 ns 3.24 ac specifications ? 10 mb/s jabber timing parameter description notes min typ max units t2.20.1 jabber activation time 85 ms t2.20.2 jabber deactivation time 500 ms copyright ? 2008 ? 2009, texas instruments incorporated electrical specifications 25 submit documentation feedback product folder links: DP83849IF tx_en tx_clk col t2.19.2 t2.19.1 t2.18.1 idle 1 0 1 pmd input pair rx_clk crs t2.20.1 t2.20.2 tx e pmd output col pair
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 3.25 ac specifications ? 10base-t normal link pulse timing (1) parameter description notes min typ max units t2.21.1 pulse width 100 ns t2.21.2 pulse period 16 ms (1) these specifications represent transmit timings. 3.26 ac specifications ? auto-negotiation fast link pulse (flp) timing (1) parameter description notes min typ max units t2.22.1 clock, data pulse width 100 ns t2.22.2 clock pulse to clock pulse 125 s period t2.22.3 clock pulse to data pulse data = 1 62 s period t2.22.4 burst width 2 ms t2.22.5 flp burst to flp burst period 16 ms (1) these specifications represent transmit timings. 3.27 ac specifications ? 100base-tx signal detect timing (1) parameter description notes min typ max units t2.23.1 sd internal turn-on time 1 ms t2.23.2 sd internal turn-off time 350 s (1) the signal amplitude on pmd input pair must be tp-pmd compliant. 26 electrical specifications copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF pmd input pair sd+ internal t2.23.1 t2.23.2 t.2.22.2 t2.22.1 fast link pulse(s) t2.22.1 t2.22.3 clock pulse data pulse clock pulse flp burst flp burst t2.22.5 t2.22.4 t2.21.2 t2.21.1 normal link pulse(s)
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 3.28 ac specifications ? 100 mb/s internal loopback timing (1) (2) parameter description notes min typ max units t2.24.1 tx_en to rx_dv loopback 100 mb/s internal loopback mode 240 ns (1) measurement is made from the first rising edge of tx_clk after assertion of tx_en. (2) due to the nature of the descrambler function, all 100base-tx loopback modes will cause an initial ? dead-time ? of up to 550 s during which time no data will be present at the receive mii outputs. the 100base-tx timing specified is based on device delays after the initial 550 s ? dead-time ? . copyright ? 2008 ? 2009, texas instruments incorporated electrical specifications 27 submit documentation feedback product folder links: DP83849IF tx_clk tx_en txd[3:0] crs rx_clk rx-dv rxd[3:0] t2.24.1
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 3.29 ac specifications ? 10 mb/s internal loopback timing (1) parameter description notes min typ max units t2.25.1 tx_en to rx_dv loopback 10 mb/s internal loopback mode 2 s (1) measurement is made from the first rising edge of tx_clk after assertion of tx_en. 3.30 ac specifications ? rmii transmit timing parameter description notes min typ max units t2.26.1 x1 clock period 50 mhz reference clock 20 ns t2.26.2 txd[1:0], tx_en, data setup to x1 rising 4 ns t2.26.3 txd[1:0], tx_en, data hold from x1 rising 2 ns t2.26.4 x1 clock to pmd output pair latency (100mb) 100base-tx or 100base-fx 11 bits 28 electrical specifications copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF symbol t2.26.1 t2.26.3 t2.26.2 t2.26.4 x1 txd[1:0] tx_en pmd output pair valid data tx_clk tx_en txd[3:0] crs rx_clk rx-dv rxd[3:0] t2.25.1
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 3.31 ac specifications ? rmii receive timing (1) (2) (3) (4) parameter description notes min typ max units t2.27.1 x1 clock period 50 mhz reference clock 20 ns t2.27.2 rxd[1:0], crs_dv, rx_dv and 2 14 ns rx_er output delay from x1 rising t2.27.3 crs on delay (100mb) (5) 100base-tx mode 18.5 bits 100base-fx mode 9 t2.27.4 crs off delay (100mb) (5) 100base-tx mode 27 bits 100base-fx mode 17 t2.27.5 rxd[1:0] and rx_er latency 100base-tx mode 38 bits (100mb) 100base-fx mode 27 (1) per the rmii specification, output delays assume a 25pf load. (2) crs_dv is asserted asynchronously in order to minimize latency of control signals through the phy. crs_dv may toggle synchronously at the end of the packet to indicate crs deassertion. (3) rx_dv is synchronous to x1. while not part of the rmii specification, this signal is provided to simplify recovery of receive data. (4) receive latency is measured from the first bit of the symbol pair on the pmd receive pair. typical values are with the elasticity buffer set to the default value (01). (5) crs on delay is measured from the first bit of the jk symbol on the pmd receive pair to initial assertion of crs_dv. copyright ? 2008 ? 2009, texas instruments incorporated electrical specifications 29 submit documentation feedback product folder links: DP83849IF data idle data (j/k) (tr) t2.27.4 t2.27.1 t2.27.5 t2.27.3 t2.27.2 t2.27.2 t2.27.2 t2.27.2 pmd input pair x1 rx_dv crs_dv rxd[1:0] rx_er
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 3.32 ac specifications ? single clock mii (scmii) transmit timing (1) parameter description notes min typ max units t2.28.1 x1 clock period 25 mhz reference clock 40 ns t2.28.2 txd[3:0], tx_en data setup to x1 rising 4 ns t2.28.3 txd[3:0], tx_en data hold from x1 rising 2 ns t2.28.4 x1 clock to pmd output pair 100base-tx or 100base-fx 13 bits latency (100mb) (1) latency measurement is made from the x1 rising edge to the first bit of symbol. 3.33 ac specifications ? single clock mii (scmii) receive timing (1) (2) (3) parameter description notes min typ max units t2.29.1 x1 clock period 25 mhz reference clock 40 ns t2.29.2 rxd[3:0], rx_dv and rx_er output delay from x1 rising 2 18 ns t2.29.3 crs on delay (100mb) (4) 100base-tx mode 19 bits 100base-fx mode 9 t2.29.4 crs off delay (100mb) (5) 100base-tx mode 26 bits 100base-fx mode 16 t2.29.5 rxd[1:0] and rx_er latency (100mb) 100base-tx mode 56 bits 100base-fx mode 46 (1) crs is asserted and deasserted asynchronously relative to the reference clock. (2) output delays assume a 25pf load. (3) receive latency is measured from the first bit of the symbol pair on the pmd receive pair. typical values are with the elasticity buffer set to the default value (01). (4) crs on delay is measured from the first bit of the jk symbol on the pmd receive pair to assertion of crs_dv. (5) crs_off delay is measured from the first bit of the tr symbol on the pmd receive pair to deassertion of crs_dv. 30 electrical specifications copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF data idle data (j/k) (tr) t2.29.4 t2.29.1 t2.29.5 t2.29.3 t2.29.2 t2.29.2 pmd input pair x1 crs rx_dv rxd[1:0] rx_er symbol t2.28.1 t2.28.3 t2.28.2 t2.28.4 x1 txd[3:0] tx_en pmd output pair valid data
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 3.34 ac specifications ? isolation timing parameter description notes min typ max units t2.30.1 from software clear of bit 10 in the bmcr register to the 100 s transition from isolate to normal mode 3.35 ac specifications ? clk2mac timing (1) parameter description notes min typ max units t2.31.1 clk2mac high/low time mii mode 20 ns rmii mode 10 ns t2.31.2 clk2mac propagation delay relative to x1 8 ns (1) clk2mac characteristics are dependent upon the x1 input characteristics. 3.36 ac specifications ? 100 mb/s x1 to tx_clk timing parameter description notes min typ max units t2.32.1 x1 to tx_clk delay (1) 100 mb/s normal mode 0 5 ns (1) x1 to tx_clk timing is provided to support devices that use x1 instead of tx_clk as the reference for transmit mll data. copyright ? 2008 ? 2009, texas instruments incorporated electrical specifications 31 submit documentation feedback product folder links: DP83849IF t2.31.1 t2.31.1 t2.31.2 x1 clk2mac normal isolate t2.30.1 mode clear bit 10 of bmcr (return to normal operation from isolate mode)
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 4 configuration this section includes information on the various configuration options available with the DP83849IF. the configuration options described below include: ? media configuration ? auto-negotiation ? phy address and leds ? half duplex vs. full duplex ? isolate mode ? loopback mode ? bist 4.1 media configuration the DP83849IF supports both twister pair (100base-tx and 10base-t) and fiber (100base-fx) media. each port may be independently configured for twisted pair (tp) or fiber (fx) operation by strap option or by register access. at power-up/reset, the state of the col_a and col_b pins will select the media for ports a and b respectively. the default selection is tp mode, while an external pull-up will select fx mode of operation. strapping a port into fx mode also automatically sets the far-end fault enable, bit 3 of pcsr (16h), the scramble bypass, bit 1 of pcsr (16h) and the descrambler bypass, bit 0 of pcsr (16h). in addition, the media selection may be controlled by writing to bit 6, fx_en, of pcsr (16h). 4.2 auto-negotiation the auto-negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest performance mode of operation supported by both devices. fast link pulse (flp) bursts provide the signalling used to communicate auto-negotiation abilities between two devices at each end of a link segment. for further detail regarding auto-negotiation, refer to clause 28 of the ieee 802.3u specification. the DP83849IF supports four different ethernet protocols (10 mb/s half duplex, 10 mb/s full duplex, 100 mb/s half duplex, and 100 mb/s full duplex), so the inclusion of auto-negotiation ensures that the highest performance protocol will be selected based on the advertised ability of the link partner. the auto-negotiation function within the DP83849IF can be controlled either by internal register access or by the use of the an_en, an1 and an0 pins. 4.2.1 auto-negotiation pin control the state of an_en, an0 and an1 determines whether the DP83849IF is forced into a specific mode or auto-negotiation will advertise a specific ability (or set of abilities) as given in table 4-1 . these pins allow configuration options to be selected without requiring internal register access. the state of an_en, an0 and an1, upon power-up/reset, determines the state of bits [8:5] of the anar register. the auto-negotiation function selected at power-up or reset can be changed at any time by writing to the basic mode control register (bmcr) at address 00h. 32 configuration copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 4-1. auto-negotiation modes an_en an1 an0 forced mode 0 0 0 10base-t, half-duplex 0 0 1 10base-t, full-duplex 0 1 0 100base-tx, half-duplex 0 1 1 100base-tx, full-duplex an_en an1 an0 advertised mode 1 0 0 10base-t, half/full-duplex 1 0 1 100base-tx, half/full-duplex 1 1 0 10base-t half-duplex 100base-tx, half-duplex 1 1 1 10base-t, half/full-duplex 100base-tx, half/full-duplex 4.2.2 auto-negotiation register control when auto-negotiation is enabled, the DP83849IF transmits the abilities programmed into the auto- negotiation advertisement register (anar) at address 04h via flp bursts. any combination of 10 mb/s, 100 mb/s, half-duplex, and full duplex modes may be selected. auto-negotiation priority resolution: 1. 100base-tx full duplex (highest priority) 2. 100base-tx half duplex 3. 10base-t full duplex 4. 10base-t half duplex (lowest priority) the basic mode control register (bmcr) at address 00h provides control for enabling, disabling, and restarting the auto-negotiation process. when auto-negotiation is disabled, the speed selection bit in the bmcr controls switching between 10 mb/s or 100 mb/s operation, and the duplex mode bit controls switching between full duplex operation and half duplex operation. the speed selection and duplex mode bits have no effect on the mode of operation when the auto-negotiation enable bit is set. the link speed can be examined through the phy status register (physts) at address 10h after a link is achieved. the basic mode status register (bmsr) indicates the set of available abilities for technology types, auto- negotiation ability, and extended register capability. these bits are permanently set to indicate the full functionality of the DP83849IF (only the 100base-t4 bit is not set since the DP83849IF does not support that function). the bmsr also provides status on: ? whether or not auto-negotiation is complete ? whether or not the link partner is advertising that a remote fault has occurred ? whether or not valid link has been established ? support for management frame preamble suppression the auto-negotiation advertisement register (anar) indicates the auto-negotiation abilities to be advertised by the DP83849IF. all available abilities are transmitted by default, but any ability can be suppressed by writing to the anar. updating the anar to suppress an ability is one way for a management agent to change (restrict) the technology that is used. the auto-negotiation link partner ability register (anlpar) at address 05h is used to receive the base link code word as well as all next page code words during the negotiation. furthermore, the anlpar will be updated to either 0081h or 0021h for parallel detection to either 100 mb/s or 10 mb/s respectively. copyright ? 2008 ? 2009, texas instruments incorporated configuration 33 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com the auto-negotiation expansion register (aner) indicates additional auto-negotiation status. the aner provides status on: ? whether or not a parallel detect fault has occurred ? whether or not the link partner supports the next page function ? whether or not the DP83849IF supports the next page function ? whether or not the current page being exchanged by auto-negotiation has been received ? whether or not the link partner supports auto-negotiation 4.2.3 auto-negotiation parallel detection the DP83849IF supports the parallel detection function as defined in the ieee 802.3u specification. parallel detection requires both the 10 mb/s and 100 mb/s receivers to monitor the receive signal and report link status to the auto-negotiation function. auto-negotiation uses this information to configure the correct technology in the event that the link partner does not support auto-negotiation but is transmitting link signals that the 100base-tx or 10base-t pmas recognize as valid link signals. if the DP83849IF completes auto-negotiation as a result of parallel detection, bits 5 and 7 within the anlpar register will be set to reflect the mode of operation present in the link partner. note that bits 4:0 of the anlpar will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field. software may determine that negotiation completed via parallel detection by reading a zero in the link partner auto-negotiation able bit once the auto-negotiation complete bit is set. if configured for parallel detect mode and any condition other than a single good link occurs then the parallel detect fault bit will be set. 4.2.4 auto-negotiation restart once auto-negotiation has completed, it may be restarted at any time by setting bit 9 (restart auto- negotiation) of the bmcr to one. if the mode configured by a successful auto-negotiation loses a valid link, then the auto-negotiation process will resume and attempt to determine the configuration for the link. this function ensures that a valid configuration is maintained if the cable becomes disconnected. a renegotiation request from any entity, such as a management agent, will cause the DP83849IF to halt any transmit data and link pulse activity until the break_link_timer expires (~1500 ms). consequently, the link partner will go into link fail and normal auto-negotiation resumes. the DP83849IF will resume auto- negotiation after the break_link_timer has expired by issuing flp (fast link pulse) bursts. 4.2.5 enabling auto-negotiation via software it is important to note that if the DP83849IF has been initialized upon power-up as a non-auto-negotiating device (forced technology), and it is then required that auto-negotiation or re-auto-negotiation be initiated via software, bit 12 (auto-negotiation enable) of the basic mode control register (bmcr) must first be cleared and then set for any auto-negotiation function to take effect. 4.2.6 auto-negotiation complete time parallel detection and auto-negotiation take approximately 2-3 seconds to complete. in addition, auto- negotiation with next page should take approximately 2-3 seconds to complete, depending on the number of next pages sent. refer to clause 28 of the ieee 802.3u standard for a full description of the individual timers related to auto-negotiation. 34 configuration copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 4.3 auto-mdix when enabled, this function utilizes auto-negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appropriate mdi pair for mdi/mdix operation. the function uses a random seed to control switching of the crossover circuitry. this implementation complies with the corresponding ieee 802.3 auto-negotiation and crossover specifications. auto-mdix is enabled by default and can be configured via strap or via phycr (19h) register, bits [15:14]. neither auto-negotiation nor auto-mdix is required to be enabled in forcing crossover of the mdi pairs. forced crossover can be achieved through the force_mdix bit, bit 14 of phycr (19h) register. note auto-mdix will not work in a forced mode of operation. 4.4 phy address the 4 phy address inputs pins are shown below. table 4-2. phy address mapping pin # phyad function rxd function 4 phyad1 rxd0_a 5 phyad2 rxd1_a 58 phyad3 rxd0_b 57 phyad4 rxd1_b the DP83849IF provides four address strap pins for determining the phy addresses for ports a and b of the device. the 4 address strap pins provide the upper four bits of the phy address. the lowest bit of the phy address is dependent on the port. port a has a value of 0 for the phy address bit 0 while port b has a value of 1. the phy address strap input pins are shown in table 4-2 . the phy address strap information is latched into the phycr register (address 19h, bits [4:0]) at device power-up and hardware reset. the phy address pins are shared with the rxd pins. each DP83849IF or port sharing an mdio bus in a system must have a unique physical address. the DP83849IF supports phy address strapping of port a to even values 0 ( < 0000_0 > ) through 30 ( < 1111_0 > ). port b is strapped to odd values 1 ( < 0000_1 > ) through 31 ( < 1111_1 > ). note that port b address is always 1 greater than port a address. for further detail relating to the latch-in timing requirements of the phy address pins, as well as the other hardware configuration pins, refer to the reset summary in section 8 . refer to figure 4-1 for an example of a phyad connection to external components. in this example, the phyad strapping results in address 00010 (02h) for port a and address 00011 (03h) for port b. 4.4.1 mii isolate mode the DP83849IF can be put into mii isolate mode by writing to bit 10 of the bmcr register. when in the mii isolate mode, the DP83849IF does not respond to packet data present at txd[3:0], tx_en inputs and presents a high impedance on the tx_clk, rx_clk, rx_dv, rx_er, rxd[3:0], col, and crs outputs. when in isolate mode, the DP83849IF will continue to respond to all management transactions. while in isolate mode, the pmd output pair will not transmit packet data but will continue to source 100base-tx scrambled idles or 10base-t normal link pulses. copyright ? 2008 ? 2009, texas instruments incorporated configuration 35 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com the DP83849IF can auto-negotiate or parallel detect to a specific technology depending on the receive signal at the pmd input pair. a valid link can be established for the receiver even when the DP83849IF is in isolate mode. figure 4-1. phyad strapping example 4.5 led interface the DP83849IF supports three configurable light emitting diode (led) pins for each port. several functions can be multiplexed onto the three leds using three different modes of operation. the led operation mode can be selected by writing to the led_cfg[1:0] register bits in the phy control register (phycr) at address 19h, bits [6:5]. in addition, led_cfg[0] for each port can be set by a strap option on the crs_a and crs_b pins. led_cfg[1] is only controllable through register access and cannot be set by as strap pin. see table 4-3 for led mode selection. table 4-3. led mode selection mode led_cfg[1] led_cfg[0] led_link led_speed led_act/led_col 1 don't care 1 on for good link on in 100 mb/s on for activity off for no link off in 10 mb/s off for no activity 2 0 0 on for good link on in 100 mb/s on for collision blink for activity off in 10 mb/s off for no collision 3 1 0 on for good link on in 100 mb/s on for full duplex blink for activity off in 10 mb/s off for half duplex the led_link pin in mode 1 indicates the link status of the port. in 100base-t mode, link is established as a result of input receive amplitude compliant with the tp-pmd specifications which will result in internal generation of signal detect. a 10 mb/s link is established as a result of the reception of at least seven consecutive normal link pulses or the reception of a valid 10base-t packet. this will cause the assertion of led_link. led_link will deassert in accordance with the link loss timer as specified in the ieee 802.3 specification. the led_link pin in mode 1 will be off when no link is present. the led_link pin in mode 2 and mode 3 will be on to indicate link is good and blink to indicate activity is present on activity. the blink frequency is defined in blink_freq, bits [7:6] of register ledcr (18h). 36 configuration copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF 2.2 k : phyad1 = 1 phyad2 = 0 phyad3 = 0 phyad4 = 0 vcc rxd1_ b rxd0_b rxd 1 _ a rxd 1 _ a
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 activity is defined as configured in ledact_rx, bit 8 of register ledcr (18h). if ledact_rx is 0, activity is signaled for either transmit or receive. if ledact_rx is 1, activity is only signaled for receive. the led_speed pin indicates 10 or 100 mb/s data rate of the port. the led is on when operating in 100mb/s mode and off when operating in 10mb/s mode. the functionality of this led is independent of mode selected. the led_act/led_col pin in mode 1 indicates the presence of either transmit or receive activity. the led will be on for activity and off for no activity. in mode 2, this pin indicates the collision status of the port. the led will be on for collision and off for no collision. the led_act/led_col pin in mode 3 indicates duplex status for 10 mb/s or 100 mb/s operation. the led will be on for full duplex and off for half duplex. in 10 mb/s half duplex mode, the collision led is based on the col signal. since these led pins are also used as strap options, the polarity of the led is dependent on whether the pin is pulled up or down. 4.5.1 leds since the auto-negotiation (an) strap options share the led output pins, the external components required for strapping and led usage must be considered in order to avoid contention. specifically, when the led outputs are used to drive leds directly, the active state of each output driver is dependent on the logic level sampled by the corresponding an input upon power-up/reset. for example, if a given an input is resistively pulled low then the corresponding output will be configured as an active high driver. conversely, if a given an input is resistively pulled high, then the corresponding output will be configured as an active low driver. refer to figure 4-2 for an example of an connections to external components at port a. in this example, the an strapping results in auto-negotiation disabled with 100 full-duplex forced. the adaptive nature of the led outputs helps to simplify potential implementation issues of these dual purpose pins. figure 4-2. an strapping and led loading example copyright ? 2008 ? 2009, texas instruments incorporated configuration 37 submit documentation feedback product folder links: DP83849IF vcc 165 : 2.2 k : 165 : 165 : gnd an0_a = 1 an1_a = 1 an_en_a = 0 led _ link _ a led _speed _ led _act/led_col_a
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 4.5.2 led direct control the DP83849IF provides another option to directly control any or all led outputs through the led direct control register (ledcr), address 18h. the register does not provide read access to leds. 4.6 half duplex vs. full duplex the DP83849IF supports both half and full duplex operation at both 10 mb/s and 100 mb/s speeds. half-duplex relies on the csma/cd protocol to handle collisions and network access. in half-duplex mode, crs responds to both transmit and receive activity in order to maintain compliance with the ieee 802.3 specification. since the DP83849IF is designed to support simultaneous transmit and receive activity it is capable of supporting full-duplex switched applications with a throughput of up to 200 mb/s per port when operating in either 100base-tx or 100base-fx. because the csma/cd protocol does not apply to full-duplex operation, the DP83849IF disables its own internal collision sensing and reporting functions and modifies the behavior of carrier sense (crs) such that it indicates only receive activity. this allows a full-duplex capable mac to operate properly. all modes of operation (100base-tx, 100base-fx, 10base-t) can run either half-duplex or full-duplex. additionally, other than crs and collision reporting, all remaining mii signaling remains the same regardless of the selected duplex mode. it is important to understand that while auto-negotiation with the use of fast link pulse code words can interpret and configure to full-duplex operation, parallel detection can not recognize the difference between full and half-duplex from a fixed 10 mb/s or 100 mb/s link partner over twisted pair. as specified in the 802.3u specification, if a far-end link partner is configured to a forced full duplex 100base-tx ability, the parallel detection state machine in the partner would be unable to detect the full duplex capability of the far-end link partner. this link segment would negotiate to a half duplex 100base-tx configuration (same scenario for 10mb/s). auto-negotiation is not supported in 100base-fx operation. selection of half or full-duplex operation is controlled by bit 8 of the basic mode control register (bmcr), address 00h. if 100base-fx mode is strapped using the fx_en pin, the an0 strap value is used to set the value of bit 8 of the bmcr (00h) register. note that the other auto-negotiation strap pins (an_en and an1) are ignored in 100base-fx mode. 4.7 internal loopback the DP83849IF includes a loopback test mode for facilitating system diagnostics. the loopback mode is selected through bit 14 (loopback) of the basic mode control register (bmcr). writing 1 to this bit enables mii transmit data to be routed to the mii receive outputs. loopback status may be checked in bit 3 of the phy status register (physts). while in loopback mode the data will not be transmitted onto the media. to ensure that the desired operating mode is maintained, auto-negotiation should be disabled before selecting the loopback mode. 4.8 bist the DP83849IF incorporates an internal built-in self test (bist) circuit to accommodate in-circuit testing or diagnostics. the bist circuit can be utilized to test the integrity of the transmit and receive data paths. bist testing can be performed with the part in the internal loopback mode or externally looped back using a loopback cable fixture. the bist is implemented with independent transmit and receive paths, with the transmit block generating a continuous stream of a pseudo random sequence. the user can select a 9 bit or 15 bit pseudo random sequence from the psr_15 bit in the phy control register (phycr). the received data is compared to the generated pseudo-random data by the bist linear feedback shift register (lfsr) to determine the bist pass/fail status. 38 configuration copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 the pass/fail status of the bist is stored in the bist status bit in the phycr register. the status bit defaults to 0 (bist fail) and will transition on a successful comparison. if an error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the start/stop bit. for transmit vod testing, the packet bist continuous mode can be used to allow continuous data transmission, setting bist_cont_mode, bit 5, of cdctrl1 (1bh). the number of bist errors can be monitored through the bist error count in the cdctrl1 (1bh), bits [15:8]. copyright ? 2008 ? 2009, texas instruments incorporated configuration 39 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 5 mac interface the DP83849IF supports several modes of operation using the mii interface pins. the options are defined in the following sections and include: ? mii mode ? rmii mode ? 10 mb serial network interface (sni) ? single clock mii mode (scmii) in addition, the DP83849IF supports the standard 802.3u mii serial management interface and a flexible mii port assignment scheme. the modes of operation can be selected by strap options or register control. for rmii mode, it is required to use the strap option, since it requires a 50 mhz clock instead of the normal 25 mhz. in each of these modes, the ieee 802.3 serial management interface is operational for device configuration and status. the serial management interface of the mii allows for the configuration and control of multiple phy devices, gathering of status, error information, and the determination of the type and capabilities of the attached phy(s). 5.1 mii interface the DP83849IF incorporates the media independent interface (mii) as specified in clause 22 of the ieee 802.3u standard. this interface may be used to connect phy devices to a mac in 10/100 mb/s systems. this section describes the nibble wide mii data interface. the nibble wide mii data interface consists of a receive bus and a transmit bus each with control signals to facilitate data transfer between the phy and the upper layer (mac). 5.1.1 nibble-wide mii data interface clause 22 of the ieee 802.3u specification defines the media independent interface. this interface includes a dedicated receive bus and a dedicated transmit bus. these two data buses, along with various control and status signals, allow for the simultaneous exchange of data between the DP83849IF and the upper layer agent (mac). the receive interface consists of a nibble wide data bus rxd[3:0], a receive error signal rx_er, a receive data valid flag rx_dv, and a receive clock rx_clk for synchronous transfer of the data. the receive clock operates at either 2.5 mhz to support 10 mb/s operation modes or at 25 mhz to support 100 mb/s operational modes. the transmit interface consists of a nibble wide data bus txd[3:0], a transmit enable control signal tx_en, and a transmit clock tx_clk which runs at either 2.5 mhz or 25 mhz. additionally, the mii includes the carrier sense signal crs, as well as a collision detect signal col. the crs signal asserts to indicate the reception of data from the network or as a function of transmit data in half duplex mode. the col signal asserts as an indication of a collision which can occur during half- duplex operation when both a transmit and receive operation occur simultaneously. 5.1.2 collision detect for half duplex, a 10base-t or 100base-tx collision is detected when the receive and transmit channels are active simultaneously. collisions are reported by the col signal on the mii. if the DP83849IF is transmitting in 10 mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. this prevents a collision being reported incorrectly due to noise on the network. the col signal remains set for the duration of the collision. if a collision occurs during a receive operation, it is immediately reported by the col signal. 40 mac interface copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 when heartbeat is enabled (only applicable to 10 mb/s operation), approximately 1 s after the transmission of each packet, a signal quality error (sqe) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. sqe is reported as a pulse on the col signal of the mii. 5.1.3 carrier sense carrier sense (crs) is asserted due to receive activity, once valid data is detected via the squelch function during 10 mb/s operation. during 100 mb/s operation crs is asserted when a valid link (sd) and two non-contiguous zeros are detected on the line. for 10 or 100 mb/s half duplex operation, crs is asserted during either packet transmission or reception. for 10 or 100 mb/s full duplex operation, crs is asserted only due to receive activity. crs is deasserted following an end of packet. 5.2 reduced mii interface the DP83849IF incorporates the reduced media independent interface (rmii) as specified in the rmii specification (rev1.2) from the rmii consortium. this interface may be used to connect phy devices to a mac in 10/100 mb/s systems using a reduced number of pins. in this mode, data is transferred 2-bits at a time using the 50 mhz rmii_ref clock for both transmit and receive. the following pins are used in rmii mode: ? tx_en ? txd[1:0] ? rx_er (optional for mac) ? crs_dv ? rxd[1:0] ? x1 (rmii reference clock is 50 mhz) in addition, the rmii mode supplies an rx_dv signal which allows for a simpler method of recovering receive data without having to separate rx_dv from the crs_dv indication. this is especially useful for diagnostic testing where it may be desirable to externally loop receive mii data directly to the transmitter. the rx_er output may be used by the mac to detect error conditions. it is asserted for symbol errors received during a packet, false carrier events, and also for fifo underrun or overrun conditions. since the phy is required to corrupt receive data on an error, a mac is not required to use rx_er. it is important to note that since both digital channels in the DP83849IF share the x1/rmii_ref input, both channels must have rmii mode enabled or both channels must have rmii mode disabled. either channel may be in 10mb or 100mb mode in rmii or non-rmii mode. since the reference clock operates at 10 times the data rate for 10 mb/s operation, transmit data is sampled every 10 clocks. likewise, receive data will be generated every 10th clock so that an attached device can sample the data every 10 clocks. rmii mode requires a 50 mhz oscillator be connected to the device x1 pin. a 50 mhz crystal is not supported. to tolerate potential frequency differences between the 50 mhz reference clock and the recovered receive clock, the receive rmii function includes a programmable elasticity buffer. the elasticity buffer is programmable to minimize propagation delay based on expected packet size and clock accuracy. this allows for supporting a range of packet sizes including jumbo frames. copyright ? 2008 ? 2009, texas instruments incorporated mac interface 41 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com the elasticity buffer will force frame check sequence errors for packets which overrun or underrun the fifo. underrun and overrun conditions can be reported in the rmii and bypass register (rbr). the following table indicates how to program the elasticity buffer fifo (in 4-bit increments) based on expected max packet size and clock accuracy. it assumes both clocks (rmii reference clock and far-end transmitter clock) have the same accuracy. packet lengths can be scaled linearly based on accuracy (+/- 25ppm would allows packets twice as large). if the threshold setting must support both 10mb and 100mb operation, the setting should be made to support both speeds. table 5-1. supported packet sizes at +/-50ppm frequency accuracy latency tolerance recommended packet size at +/- 50ppm start threshold rbr[1:0] 100mb 10mb 100mb 10mb 01 (default) 2 bits 8 bits 2,400 bytes 9,600 bytes 10 6 bits 4 bits 7,200 bytes 4,800 bytes 11 10 bits 8 bits 12,000 bytes 9,600 bytes 00 14 bits 12 bits 16,800 bytes 14,400 bytes 5.3 10 mb serial network interface (sni) the DP83849IF incorporates a 10 mb serial network interface (sni) which allows a simple serial data interface for 10 mb only devices. this is also referred to as a 7-wire interface. while there is no defined standard for this interface, it is based on early 10 mb physical layer devices. data is clocked serially at 10 mhz using separate transmit and receive paths. the following pins are used in sni mode: ? tx_clk ? tx_en ? txd[0] ? rx_clk ? rxd[0] ? crs ? col 5.4 single clock mii mode single clock mii (scmii) mode allows mii operation using a single 25 mhz reference clock. normal mii mode requires three clocks, a reference clock for physical layer functions, a transmit mii clock, and a receive mii clock. similar to rmii mode, single clock mii mode requires only the reference clock. in addition to reducing the number of pins required, this mode allows the attached mac device to use only the reference clock domain. since the DP83849IF has two ports, this actually reduces the number of clocks from 6 to 1. a/c timing requirements for scmii operation are similar to the rmii timing requirements. for 10mb operation, as in rmii mode, data is sampled and driven every 10 clocks since the reference clock is at 10x the data rate. separate control bits allow enabling the transmit and receive single clock modes separately, allowing just transmit or receive to operate in this mode. control of single clock mii mode is through the rbr register. single clock mii mode incorporates the use of the rmii elasticity buffer, which is required to tolerate potential frequency differences between the 25 mhz reference clock and the recovered receive clock. settings for the elasticity buffer for scmii mode are detailed in the following table. 42 mac interface copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 5-2. supported scmii packet sizes at +/-50ppm frequency accuracy latency tolerance recommended packet size at +/- 50ppm start threshold rbr[1:0] 100mb 10mb 100mb 10mb 01 (default) 4 bits 8 bits 4,000 bytes 9,600 bytes 10 4 bits 8 bits 4,000 bytes 9,600 bytes 11 12 bits 8 bits 9,600 bytes 9,600 bytes 00 12 bits 8 bits 9,600 bytes 9,600 bytes 5.5 flexible mii port assignment the DP83849IF supports a flexible assignment scheme for each of the channels to the mii/rmii interface. either of the mii ports may be assigned to the internal channels a/b. these values are controlled by the rmii and bypass register (rbr), address 17h. transmit assignments and receive assignments can be made separately to allow even more flexibility (i.e. both channels could transmit from mii a while still allowing separate receive paths for the channels). in addition, the opposite receive channel may be used as the transmit source for each channel. as shown in figure 5-1 , channel a receive data may be used as the channel b transmit data source while channel b receive data may be used as the channel a transmit data source. for proper clock synchronization, this function requires the device be in rmii mode or single clock mii mode of operation. a configuration strap is provided on pin 56, rxd2_b/extender_en to enable this mode. figure 5-1. mii port mapping 5.5.1 rx mii port mapping note that channel a is the master of mii port a, and channel b is the master of mii port b. this means that in order for channel b to control mii port a, channel a must be configured to either control mii port b or be disabled; the reverse is also true. rx mii port mapping controls and configurations are shown in the following tables: copyright ? 2008 ? 2009, texas instruments incorporated mac interface 43 submit documentation feedback product folder links: DP83849IF channel a channel b mii port a mii port b tx rx tx rx 10base-t 10base-tx or 100base-fx 10base-t 10base-tx or 100base-fx tx rx tx rx
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com table 5-3. rx mii port mapping controls rbr[12:11] desired rx channel destination 00 normal port 01 opposite port 10 both ports 11 disabled table 5-4. rx mii port mapping configurations channel a rbr[12:11] channel b rbr[12:11] rx mii port a source rx mii port b source 00 00 channel a channel b 00 01 channel a channel b 00 10 channel a channel b 00 11 channel a disabled 01 00 channel a channel b 01 01 channel b channel a 01 10 channel b channel a 01 11 disabled channel a 10 00 channel a channel b 10 01 channel b channel a 10 10 channel a channel b 10 11 channel a channel a 11 00 disabled channel b 11 01 channel b disabled 11 10 channel b channel b 11 11 disabled disabled 5.5.2 tx mii port mapping tx mii port mapping controls and configurations are shown in the following tables: table 5-5. tx mii port mapping controls rbr[10:9] tx channel source 00 normal port 01 opposite port 10 opposite rx port 11 disabled table 5-6. tx mii port mapping configurations channel a rbr[10:9] port a tx source channel b rbr[10:9] port b tx source 00 mii port a 00 mii port b 01 mii port b 01 mii port a 10 rx channel b 10 rx channel a 11 disabled 11 disabled 44 mac interface copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 5.5.3 common flexible mii port configurations table 5-7. common flexible mii port configurations channel a channel b mode description rbr[12:9] rbr[12:9] normal 0000 0000 mii port a assigned to channel a, mii port b assigned to channel b full port swap 0101 0101 mii port a assigned to channel b, mii port b assigned to channel a extender/media converter 1110 1110 mii rx disabled, channel a transmits from channel b rx data, channel b transmits from channel a rx data broadcast tx mii port a xx00 xx01 both channels transmit from tx mii port a broadcast tx mii port b xx01 xx00 both channels transmit from tx mii port b mirror rx channel a 10xx 11xx channel a rx traffic appears on both ports mirror rx channel b 11xx 10xx channel b rx traffic appears on both ports disable port a 1111 xxxx mii port a is disabled disable port b xxxx 1111 mii port b is disabled 5.5.4 strapped extender or media converter mode the DP83849IF provides a simple strap option to automatically configure both channels for extender or media converter mode with no device register configuration necessary. the extender_en strap can be used in conjunction with the auto-negotiation straps (an_en, an0, an1), the rmii mode strap, and the fiber mode (fx_en) strap to allow many possible configurations. if extender mode is strapped but rmii mode is not, both channels will automatically be configured for single clock mii receive and transmit modes. the optional use of rmii mode in conjunction with extender mode allows flexibility in the system design. several common configurations are shown in table 5-8 . table 5-8. common strapped extender/media converter mode configurations mode auto-negotiation straps fiber mode straps 100mb copper extender both channels are forced to 100mb full duplex disabled for both channels 100mb fiber extender n/a enabled for both channels 10mb copper extender both channels are forced to 10mb full duplex disabled for both channels 100mb media converter one channel is forced to 100mb full duplex enabled for the other channel 5.5.5 notes and restrictions ? extender/media converter: both channels must be operating at the same speed (10 or 100mb). this can be accomplished using straps or channel register controls. both channels must be in full duplex mode. both channels must either be in rmii mode (rbr:rmii_en = 1) or full single clock mii mode (rbr:scmii_rx = 1 and rbr:scmii_tx = 1) to ensure synchronous operation. if only one rx to tx path is enabled, scmii_rx in the rx channel (rbr register 17h bit 7) and scmii_tx in the tx channel (rbr register 17h bit 6) must be set to 1. media conversion is only supported in 100mb mode; one channel must be in fiber mode (100base-fx) and the other channel must be in copper mode (100base-tx). ? broadcast tx mii port mode: to ensure synchronous operation, both channels must be in rmii mode (rbr register 17h bit 5 = 1) or in single clock tx mii mode (rbr register 17h bit 6 = 1). both channels must be operating at the same speed (10 or 100mb). both channels must be in full duplex mode to ensure no collisions are seen. this is because in single clock tx mii mode, a collision on one phy channel would cause both channels to send the jam pattern. copyright ? 2008 ? 2009, texas instruments incorporated mac interface 45 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com ? rmii mode: both channels must have rmii mode enabled or disabled concurrently due to the internal reference clocking scheme. in full port swap mode, channels are not required to have a common speed. ? 10base-t serial mode: this mac-side mode, also known as serial network interface (sni), may not be used when both channels share data connections (extender/media converter or broadcast tx mii port). this is due to the requirement of synchronous operation between channels, which is not supported in sni mode. ? crs assignment: when a channel is not in rmii mode, its associated crs pin is sourced from the transmitter and controlled by the tx mii port assignment, bits [10:9] of rbr (17h). when a channel is in rmii mode, the associated crs pin is sourced from the receiver and controlled by the rx mii port assignment, bits [12:11] of rbr (17h). ? output enables: flexible mii port assignment does not control signal output enables. ? test modes: test modes are not designed to be compatible with flexible mii port selection, which assumes default mii pin directions. ? led assignment: leds are associated with their respective digital channels, and therefore do not get mapped to alternate channels. for example, assertion of led_link_a indicates valid link status for channel a independent of the mii port assignment. ? straps: strap pins are always associated with their respective channel, i.e. a strap on rx_er_a is used by channel a. ? port isolate mode: each mii port ? s isolate function, bit 10 of bmcr (00h) is always associated with its respective channel, i.e. the isolate function for port a is always controlled by channel a ? s bmcr (00h). due to the various possible combinations of tx and rx port selection, it may not be advisable to place a port in isolate mode. ? energy detect and powerdown modes: the output enables for each mii port are always controlled by the respective channel energy detect and powerdown functions. these functions should be disabled whenever an mii port is in use but not assigned to its default channel. note that extender/media converter modes allow the use of energy detect and powerdown modes if the rx mii ports are not in use. 5.6 802.3u mii serial management interface 5.6.1 serial management register access the serial management mii specification defines a set of thirty-two 16-bit status and control registers that are accessible through the management interface pins mdc and mdio. the DP83849IF implements all the required mii registers as well as several optional registers. these registers are fully described in section 9 . a description of the serial management access protocol follows. 5.6.2 serial management access protocol the serial control interface consists of two pins, management data clock (mdc) and management data input/output (mdio). mdc has a maximum clock rate of 25 mhz and no minimum rate. the mdio line is bi-directional and may be shared by up to 32 devices. the mdio frame format is shown below in table 5-9 . in addition, the mdio pin requires a pull-up resistor (1.5 k ? ) which, during idle and turnaround, will pull mdio high. in order to initialize the mdio interface, the station management entity sends a sequence of 32 contiguous logic ones on mdio to provide the DP83849IF with a sequence that can be used to establish synchronization. this preamble may be generated either by driving mdio high for 32 consecutive mdc clock cycles, or by simply allowing the mdio pull-up resistor to pull the mdio pin high during which time 32 mdc clock cycles are provided. in addition 32 mdc clock cycles should be used to re-sync the device if an invalid start, opcode, or turnaround bit is detected. 46 mac interface copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 the DP83849IF waits until it has received this preamble sequence before responding to any other transaction. once the DP83849IF serial management port has been initialized no further preamble sequencing is required until after a power-on/reset, invalid start, invalid opcode, or invalid turnaround bit has occurred. the start code is indicated by a < 01 > pattern. this assures the mdio line transitions from the default idle line state. turnaround is defined as an idle bit time inserted between the register address field and the data field. to avoid contention during a read transaction, no device shall actively drive the mdio signal during the first bit of turnaround. the addressed DP83849IF drives the mdio with a zero for the second bit of turnaround and follows this with the required data. figure 5-2 shows the timing relationship between mdc and the mdio as driven/received by the station (sta) and the DP83849IF (phy) for a typical register read access. for write transactions, the station management entity writes data to the addressed DP83849IF thus eliminating the requirement for mdio turnaround. the turnaround time is filled by the management entity by inserting < 10 > . figure 5-3 shows the timing relationship for a typical mii register write access. table 5-9. typical mdio frame format mii management serial protocol < idle > < start > < op code > < device addr > < reg addr > < turnaround > < data > < idle > read operation < idle > < 01 > < 10 > < aaaaa > < rrrrr > < z0 > < xxxx xxxx xxxx xxxx > < idle > write operation < idle > < 01 > < 01 > < aaaaa > < rrrrr > < 10 > < xxxx xxxx xxxx xxxx > < idle > figure 5-2. typical mdc/mdio read operation figure 5-3. typical mdc/mdio write operation 5.6.3 serial management preamble suppression the DP83849IF supports a preamble suppression mode as indicated by a one in bit 6 of the basic mode status register (bmsr, address 01h.) if the station management entity (i.e. mac or other management controller) determines that all phys in the system support preamble suppression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction. copyright ? 2008 ? 2009, texas instruments incorporated mac interface 47 submit documentation feedback product folder links: DP83849IF z z z z register data ta idle register address (00h = bcmr) phy address (phy ad = 0ch) opcode (write) start idle mdc mdio (sta) 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 z z z z z z register data ta idle register address (00h = bcmr) phy address (phy ad = 0ch) opcode (read) start idle mdc mdio mdio (sta) (phy) z 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com the DP83849IF requires a single initialization sequence of 32 bits of preamble following hardware/software reset. this requirement is generally met by the mandatory pull-up resistor on mdio in conjunction with a continuous mdc, or the management access made to determine whether preamble suppression is supported. while the DP83849IF requires an initial preamble sequence of 32 bits for management initialization, it does not require a full 32-bit sequence between each subsequent transaction. a minimum of one idle bit between management transactions is required as specified in the ieee 802.3u specification. 5.6.4 simultaneous register write the DP83849IF incorporates a mode which allows simultaneous write access to both port a and b register blocks at the same time. this mode is selected by setting bit 15 of rmii and bypass register (rbr, address 17h) in port a. as long as this bit remains set, subsequent writes to port a will write to registers in both ports. register reads are unaffected. each port must still be read individually. 48 mac interface copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 6 architecture this section describes the operations within each transceiver module, 100base-tx and 10base-t. each operation consists of several functional blocks and described in the following: ? 100base-tx transmitter ? 100base-tx receiver ? 100base-fx operation ? 10base-t transceiver module 6.1 100base-tx transmitter the 100base-tx transmitter consists of several functional blocks which convert synchronous 4-bit nibble data, as provided by the mii, to a scrambled mlt-3 125 mb/s serial data stream. because the 100base- tx tp-pmd is integrated, the differential output pins, pmd output pair, can be directly routed to the magnetics. the block diagram in figure 6-1 . provides an overview of each functional block within the 100base-tx transmit section. the transmitter section consists of the following functional blocks: ? code-group encoder and injection block ? scrambler block (bypass option) ? nrz to nrzi encoder block ? binary to mlt-3 converter / common driver the bypass option for the functional blocks within the 100base-tx transmitter provides flexibility for applications where data conversion is not always required. the DP83849IF implements the 100base-tx transmit state machine diagram as specified in the ieee 802.3u standard, clause 24. figure 6-1. 100base-tx transmit block diagram copyright ? 2008 ? 2009, texas instruments incorporated architecture 49 submit documentation feedback product folder links: DP83849IF pmd output pair mux scrambler mlt[1:0] tx_clk txd[3:0]/ tx_en divide by 5 4b5bcode- group encoder and 5b parallel to serial bp_scf 125 mhz clock 100base-tx loopback nrz to nrzi encoder binary to mlt-3/ common driver
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com table 6-1. 4b5b code-group encoding/decoding data codes 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 a 10110 1010 b 10111 1011 c 11010 1100 d 11011 1101 e 11100 1110 f 11101 1111 idle and control codes h 00100 halt code-group - error code i 11111 inter-packet idle - 0000 (1) j 11000 first start of packet - 0101 (1) k 10001 second start of packet - 0101 (1) t 01101 first end of packet - 0000 (1) r 00111 second end of packet - 0000 (1) invalid codes v 00000 v 00001 v 00010 v 00011 v 00101 v 00110 v 01000 v 01100 (1) control code-groups i, j, k, t and r in data fields will be mapped as invalid codes, together with rx_er asserted. 6.1.1 code-group encoding and injection the code-group encoder converts 4-bit (4b) nibble data generated by the mac into 5-bit (5b) code-groups for transmission. this conversion is required to allow control data to be combined with packet data code- groups. refer to table 6-1 for 4b to 5b code-group mapping details. the code-group encoder substitutes the first 8-bits of the mac preamble with a j/k code-group pair (11000 10001) upon transmission. the code-group encoder continues to replace subsequent 4b preamble and data nibbles with corresponding 5b code-groups. at the end of the transmit packet, upon the deassertion of transmit enable signal from the mac, the code-group encoder injects the t/r code-group pair (01101 00111) indicating the end of the frame. after the t/r code-group pair, the code-group encoder continuously injects idles into the transmit data stream until the next transmit packet is detected (reassertion of transmit enable). 50 architecture copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 6.1.2 scrambler the scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100base-tx applications). by scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. without the scrambler, energy levels at the pmd and on the cable could peak beyond fcc limitations at frequencies related to repeating 5b sequences (i.e., continuous transmission of idles). the scrambler is configured as a closed loop linear feedback shift register (lfsr) with an 11-bit polynomial. the output of the closed loop lfsr is x-ord with the serial nrz data from the code-group encoder. the result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 db. the DP83849IF uses the phy_id (pins phyad [4:1]) to set a unique seed value. 6.1.3 nrz to nrzi encoder after the transmit data stream has been serialized and scrambled, the data must be nrzi encoded in order to comply with the tp-pmd standard for 100base-tx transmission over category-5 unshielded twisted pair cable. 6.1.4 binary to mlt-3 convertor the binary to mlt-3 conversion is accomplished by converting the serial binary data stream output from the nrzi encoder into two binary data streams with alternately phased logic one events. these two binary streams are then fed to the twisted pair output driver which converts the voltage to current and alternately drives either side of the transmit transformer primary winding, resulting in a mlt-3 signal. the 100base-tx mlt-3 signal sourced by the pmd output pair common driver is slew rate controlled. this should be considered when selecting ac coupling magnetics to ensure tp-pmd standard compliant transition times (3 ns < tr < 5 ns). the 100base-tx transmit tp-pmd function within the DP83849IF is capable of sourcing only mlt-3 encoded data. binary output from the pmd output pair is not possible in 100 mb/s mode. 6.2 100base-tx receiver the 100base-tx receiver consists of several functional blocks which convert the scrambled mlt-3 125 mb/s serial data stream to synchronous 4-bit nibble data that is provided to the mii. because the 100base-tx tp-pmd is integrated, the differential input pins, rd , can be directly routed from the ac coupling magnetics. see figure 6-2 for a block diagram of the 100base-tx receive function. this provides an overview of each functional block within the 100base-tx receive section. the receive section consists of the following functional blocks: ? analog front end ? digital signal processor ? signal detect ? mlt-3 to binary decoder ? nrzi to nrz decoder ? serial to parallel ? descrambler ? code group alignment ? 4b/5b decoder ? link integrity monitor ? bad ssd detection copyright ? 2008 ? 2009, texas instruments incorporated architecture 51 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 6.2.1 analog front end in addition to the digital equalization and gain control, the DP83849IF includes analog equalization and gain control in the analog front end. the analog equalization reduces the amount of digital equalization required in the dsp. 6.2.2 digital signal processor the digital signal processor includes adaptive equalization with gain control and base line wander compensation. figure 6-2. 100base-tx receive block diagram 52 architecture copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF 4b/5b decoder descrambler rx_clk rxd[3:0] / rx_er code group alignment serial to parallel rx_dv/crs rd +/- digital signal processor analog front end signal detect mlt-3 to binary decoder nrzi to nrz decoder link integrity monitor rx_data valid ssd detect
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 6.2.2.1 digital adaptive equalization and gain control when transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. in high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream. this variation in signal attenuation caused by frequency variations must be compensated to ensure the integrity of the transmission. in order to ensure quality transmission when employing mlt-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. the selection of long cable lengths for a given implementation, requires significant compensation which will over- compensate for shorter, less attenuating lengths. conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. the DP83849IF utilizes an extremely robust equalization scheme referred as ? digital adaptive equalization. ? the digital equalizer removes isi (inter symbol interference) from the receive data stream by continuously adapting to provide a filter with the inverse frequency response of the channel. equalization is combined with an adaptive gain control stage. this enables the receive 'eye pattern' to be opened sufficiently to allow very reliable data recovery. the curves given in figure 6-3 illustrate attenuation at certain frequencies for given cable lengths. this is derived from the worst case frequency vs. attenuation figures as specified in the eia/tia bulletin tsb-36. these curves indicate the significant variations in signal attenuation that must be compensated for by the receive adaptive equalization circuit. figure 6-3. eia/tia attenuation vs. frequency for 0, 50, 100, 130 & 150 meters of cat 5 cable copyright ? 2008 ? 2009, texas instruments incorporated architecture 53 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 6.2.2.2 base line wander compensation figure 6-4. 100base-tx blw event the DP83849IF is completely ansi tp-pmd compliant and includes base line wander (blw) compensation. the blw compensation block can successfully recover the tp-pmd defined ? killer ? pattern. blw can generally be defined as the change in the average dc content, relatively short period over time, of an ac coupled digital transmission over a given transmission medium. (i.e., copper wire). blw results from the interaction between the low frequency components of a transmitted bit stream and the frequency response of the ac coupling component(s) within the transmission system. if the low frequency content of the digital bit stream goes below the low frequency pole of the ac coupling transformers then the droop characteristics of the transformers will dominate resulting in potentially serious blw. the digital oscilloscope plot provided in figure 6-4 illustrates the severity of the blw event that can theoretically be generated during 100base-tx packet transmission. this event consists of approximately 800 mv of dc offset for a period of 120 ms. left uncompensated, events such as this can cause packet loss. 6.2.3 signal detect the signal detect function of the DP83849IF is incorporated to meet the specifications mandated by the ansi fddi tp-pmd standard as well as the ieee 802.3 100base-tx standard for both voltage thresholds and timing parameters. note that the reception of normal 10base-t link pulses and fast link pulses per ieee 802.3u auto- negotiation by the 100base-tx receiver do not cause the DP83849IF to assert signal detect. 6.2.4 mlt-3 to nrzi decoder the DP83849IF decodes the mlt-3 information from the digital adaptive equalizer block to binary nrzi data. 6.2.5 nrzi to nrz in a typical application, the nrzi to nrz decoder is required in order to present nrz formatted data to the descrambler. 6.2.6 serial to parallel the 100base-tx receiver includes a serial to parallel converter which supplies 5-bit wide data symbols to the pcs rx state machine. 54 architecture copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 6.2.7 descrambler a serial descrambler is used to de-scramble the received nrz data. the descrambler has to generate an identical data scrambling sequence (n) in order to recover the original unscrambled data (ud) from the scrambled data (sd) as represented in the equations: synchronization of the descrambler to the original scrambling sequence (n) is achieved based on the knowledge that the incoming scrambled data stream consists of scrambled idle data. after the descrambler has recognized 12 consecutive idle code-groups, where an unscrambled idle code-group in 5b nrz is equal to five consecutive ones (11111), it will synchronize to the receive data stream and generate unscrambled data in the form of unaligned 5b code-groups. in order to maintain synchronization, the descrambler must continuously monitor the validity of the unscrambled data that it generates. to ensure this, a line state monitor and a hold timer are used to constantly monitor the synchronization status. upon synchronization of the descrambler the hold timer starts a 722 s countdown. upon detection of sufficient idle code-groups (58 bit times) within the 722 s period, the hold timer will reset and begin a new countdown. this monitoring operation will continue indefinitely given a properly operating network connection with good signal integrity. if the line state monitor does not recognize sufficient unscrambled idle code-groups within the 722 s period, the entire descrambler will be forced out of the current state of synchronization and reset in order to re-acquire synchronization. 6.2.8 code-group alignment the code-group alignment module operates on unaligned 5-bit data from the descrambler (or, if the descrambler is bypassed, directly from the nrzi/nrz decoder) and converts it into 5b code-group data (5 bits). code-group alignment occurs after the j/k code-group pair is detected. once the j/k code-group pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary. 6.2.9 4b/5b decoder the code-group decoder functions as a look up table that translates incoming 5b code-groups into 4b nibbles. the code-group decoder first detects the j/k code-group pair preceded by idle code-groups and replaces the j/k with mac preamble. specifically, the j/k 10-bit code-group pair is replaced by the nibble pair (0101 0101). all subsequent 5b code-groups are converted to the corresponding 4b nibbles for the duration of the entire packet. this conversion ceases upon the detection of the t/r code-group pair denoting the end of stream delimiter (esd) or with the reception of a minimum of two idle code-groups. 6.2.10 100base-tx link integrity monitor the 100 base tx link monitor ensures that a valid and stable link is established before enabling both the transmit and receive pcs layer. signal detect must be valid for 395us to allow the link monitor to enter the 'link up' state, and enable the transmit and receive functions. 6.2.11 bad ssd detection a bad start of stream delimiter (bad ssd) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /j/k. if this condition is detected, the DP83849IF will assert rx_er and present rxd[3:0] = 1110 to the mii for the cycles that correspond to received 5b code-groups until at least two idle code groups are detected. in addition, the false carrier sense counter register (fcscr) will be incremented by one. once at least two idle code groups are detected, rx_er and crs become de-asserted. copyright ? 2008 ? 2009, texas instruments incorporated architecture 55 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 6.3 100base-fx operation the DP83849IF provides ieee 802.3 compliant 100base-fx operation. configuration of fx mode is via strap option, or through the register interface. 6.3.1 100base-fx transmit in 100base-fx mode, the device transmit pins connect to an industry standard fiber transceiver with pecl signalling through a capacitively coupled circuit. in fx mode, the device bypasses the scrambler and the mlt3 encoder. this allows for the transmission of serialized 5b4b encoded nrzi data at 125 mhz. the only added functionality from 100base-tx is the support for far-end fault data generation. 6.3.2 100base-fx receive in 100base-fx mode, the device receive pins connect to an industry standard fiber transceiver with pecl signalling through a capacitively coupled circuit. in fx mode, the device bypasses mlt3 decoder and the descrambler. this allows for the reception of serialized 5b4b encoded nrzi data at 125 mhz. the only added functionality for 100base-fx from 100base-tx is the support of far-end fault detection. 6.3.3 far-end fault since 100base-fx does not support auto-negotiation, a far-end fault facility is included which allows for detection of link failures. when no signal is being received as determined by the signal detect function, the device sends a far- end fault indication to the far-end peer. the far-end fault indication is comprised of 3 or more repeating cycles, each consisting of 84 one ? s followed by 1 zero. the pattern is such that it will not satisfy the 100base-x carrier sense mechanism, but is easily detected as the fault indication. the pattern will be transparent to devices that do not support far-end fault. the far-end fault detection process continuously monitors the receive data stream for the far-end fault indication. when detected, the link monitor is forced to deassert link status. this causes the device to transmit idle ? s on its transmit path. 6.4 10base-t transceiver module the 10base-t transceiver module is ieee 802.3 compliant. it includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. an external filter is not required on the 10base-t interface since this is integrated inside the DP83849IF. this section focuses on the general 10base-t system level operation. 6.4.1 operational modes the DP83849IF has two basic 10base-t operational modes: ? half duplex mode ? full duplex mode 6.4.1.1 half duplex mode in half duplex mode the DP83849IF functions as a standard ieee 802.3 10base-t transceiver supporting the csma/cd protocol. 56 architecture copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 6.4.1.2 full duplex mode in full duplex mode the DP83849IF is capable of simultaneously transmitting and receiving without asserting the collision signal. the DP83849IF's 10 mb/s endec is designed to encode and decode simultaneously. 6.4.2 smart squelch the smart squelch is responsible for determining when valid data is present on the differential receive inputs. the DP83849IF implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. smart squelch operation is independent of the 10base-t operational mode. the squelch circuitry employs a combination of amplitude and timing measurements (as specified in the ieee 802.3 10bse-t standard) to determine the validity of data on the twisted pair inputs (refer to figure 6-5 ). the signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. once this first squelch level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. finally the signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will not be rejected. this checking procedure results in the loss of typically three preamble bits at the beginning of each packet. only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. at this time, the smart squelch circuitry is reset. valid data is considered to be present until the squelch level has not been generated for a time longer than 150 ns, indicating the end of packet. once good data has been detected, the squelch levels are reduced to minimize the effect of noise causing premature end of packet detection. figure 6-5. 10base-t twisted pair smart squelch operation 6.4.3 collision detection and sqe when in half duplex, a 10base-t collision is detected when the receive and transmit channels are active simultaneously. collisions are reported by the col signal on the mii. collisions are also reported when a jabber condition is detected. the col signal remains set for the duration of the collision. if the phy is receiving when a collision is detected it is reported immediately (through the col pin). copyright ? 2008 ? 2009, texas instruments incorporated architecture 57 submit documentation feedback product folder links: DP83849IF start of packet end of packet <150 ns <150 ns >150 ns vsq+ vsq- vsq-(reduced) vsq+(reduced)
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com when heartbeat is enabled, approximately 1 s after the transmission of each packet, a signal quality error (sqe) signal of approximately 10-bit times is generated to indicate successful transmission. sqe is reported as a pulse on the col signal of the mii. the sqe test is inhibited when the phy is set in full duplex mode. sqe can also be inhibited by setting the heartbeat_dis bit in the 10btscr register. 6.4.4 carrier sense carrier sense (crs) may be asserted due to receive activity once valid data is detected via the squelch function. for 10 mb/s half duplex operation, crs is asserted during either packet transmission or reception. for 10 mb/s full duplex operation, crs is asserted only during receive activity. crs is deasserted following an end of packet. 6.4.5 normal link pulse detection/generation the link pulse generator produces pulses as defined in the ieee 802.3 10base-t standard. each link pulse is nominally 100 ns in duration and transmitted every 16 ms in the absence of transmit data. link pulses are used to check the integrity of the connection with the remote end. if valid link pulses are not received, the link detector disables the 10base-t twisted pair transmitter, receiver and collision detection functions. when the link integrity function is disabled (force_link_10 of the 10btscr register), a good link is forced and the 10base-t transceiver will operate regardless of the presence of link pulses. 6.4.6 jabber function the jabber function monitors the DP83849IF's output and disables the transmitter if it attempts to transmit a packet of longer than legal size. a jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 85 ms. once disabled by the jabber function, the transmitter stays disabled for the entire time that the endec module's internal transmit enable is asserted. this signal has to be de-asserted for approximately 500 ms (the ? unjab ? time) before the jabber function re-enables the transmit outputs. the jabber function is only relevant in 10base-t mode. 6.4.7 automatic link polarity detection and correction the DP83849IF's 10base-t transceiver module incorporates an automatic link polarity detection circuit. when three consecutive inverted link pulses are received, bad polarity is reported. a polarity reversal can be caused by a wiring error at either end of the cable, usually at the main distribution frame (mdf) or patch panel in the wiring closet. the bad polarity condition is latched in the 10btscr register. the DP83849IF's 10base-t transceiver module corrects for this error internally and will continue to decode received data correctly. this eliminates the need to correct the wiring error immediately. 6.4.8 transmit and receive filtering external 10base-t filters are not required when using the DP83849IF, as the required signal conditioning is integrated into the device. only isolation transformers and impedance matching resistors are required for the 10base-t transmit and receive interface. the internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30 db. 58 architecture copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 6.4.9 transmitter the encoder begins operation when the transmit enable input (tx_en) goes high and converts nrz data to pre-emphasized manchester data for the transceiver. for the duration of tx_en, the serialized transmit data (txd) is encoded for the transmit-driver pair (pmd output pair). txd must be valid on the rising edge of transmit clock (tx_clk). transmission ends when tx_en deasserts. the last transition is always positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the bit cell if the last bit is a zero. 6.4.10 receiver the decoder detects the end of a frame when no additional mid-bit transitions are detected. within one and a half bit times after the last bit, carrier sense is de-asserted. receive clock stays active for five more bit times after crs goes low, to ensure the receive timings of the controller. copyright ? 2008 ? 2009, texas instruments incorporated architecture 59 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 7 design guidelines 7.1 tpi network circuit figure 7-1 shows the recommended circuit for a 10/100 mb/s twisted pair interface. below is a partial list of recommended transformers. it is important that the user realize that variations with pcb and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application. pulse h1102 pulse h2019 belfuse s558-5999-u7 halo tg110-s050n2rl figure 7-1. 10/100 mb/s twisted pair interface 60 design guidelines copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF 4b/5b decoder descrambler rx_clk rxd[3:0] / rx_er code group alignment serial to parallel rx_dv/crs rd +/- digital signal processor analog front end signal detect mlt-3 to binary decoder nrzi to nrz decoder link integrity monitor rx_data valid ssd detect
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 7.2 fiber network circuit figure 7-2 shows the recommended circuit for a 100 mb/s fiber pair interface. figure 7-2. 100 mb/s fiber pair interface 7.3 esd protection typically, esd precautions are predominantly in effect when handling the devices or board before being installed in a system. in those cases, strict handling procedures need be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic esd events. after the system is assembled, internal components are less sensitive from esd events. the network interface pins are more susceptible to esd events. copyright ? 2008 ? 2009, texas instruments incorporated design guidelines 61 submit documentation feedback product folder links: DP83849IF 50 : 50 : 130 : 130 : 0.1 p f 0.1 p f vdd 130 : 130 : 130 : fiber transceiver all values are typical abd are +/- 1% place resistors and capacitors close to the device place resistors close to the fiber transceiver fxtdp fxtdm fxsd fxrdp fxrdm 80 : 80 : 80 : 80 : 80 : td+ td- sd rd+ rd-
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 7.4 clock in (x1) requirements the DP83849IF supports an external cmos level oscillator source or a crystal resonator device. oscillator if an external clock source is used, x1 should be tied to the clock source and x2 should be left floating. specifications for cmos oscillators: 25 mhz in mii mode and 50 mhz in rmii mode are listed in table 7-1 and table 7-2 . crystal a 25 mhz, parallel, 20 pf load crystal resonator should be used if a crystal source is desired. figure 7-3 shows a typical connection for a crystal resonator circuit. the load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. the oscillator circuit is designed to drive a parallel resonance at cut crystal with a minimum drive level of 100mw and a maximum of 500 w. if a crystal is specified for a lower drive level, a current limiting resistor should be placed in series between x2 and the crystal. as a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, c l1 and c l2 should be set at 33 pf, and r 1 should be set at 0 ? . specification for 25 mhz crystal are listed in table 7-3 . figure 7-3. crystal oscillator circuit table 7-1. 25 mhz oscillator specification parameter min typ max units condition frequency 25 mhz frequency tolerance 50 ppm operational temperature frequency stability 50 ppm 1 year aging rise / fall time 6 nsec 20% - 80% jitter 800 (1) psec short term jitter 800 (1) psec long term symmetry 40% 60% duty cycle (1) this limit is provided as a guide for component selection and not ensured by production testing. refer to an-1548, ? phyter 100 base- tx reference clock jitter tolerance, ? for details on jetter performance. 62 design guidelines copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF x1 x2 r1 cl2 cl1
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 7-2. 50 mhz oscillator specification parameter min typ max units condition frequency 50 mhz frequency tolerance 50 ppm operational temperature frequency stability 50 ppm operational temperature rise / fall time 6 nsec 20% - 80% jitter 800 (1) psec short term jitter 800 (1) psec long term symmetry 40% 60% duty cycle (1) this limit is provided as a guide for component selection and not ensured by production testing. refer to an-1548, ? phyter 100 base- tx reference clock jitter tolerance, ? for details on jetter performance. table 7-3. 25 mhz crystal specification parameter min typ max units condition frequency 25 mhz frequency tolerance 50 ppm operational temperature frequency stability 50 ppm 1 year aging load capacitance 25 40 pf 7.5 power feedback circuit to ensure correct operation for the DP83849IF, parallel caps with values of 10 f and 0.1 f should be placed close to pin 31 ( pfbout ) of the device. pin 7 ( pfbin1 ), pin 28 ( pfbin2 ), pin 34 ( pfbin3 ) and pin 54 ( pfbin4 ) must be connected to pin 31 ( pfbout ), each pin requires a small capacitor (.1 f). see figure 7-4 below for proper connections. figure 7-4. power feedback connection 7.6 power down/interrupt the power down and interrupt functions are multiplexed on pin 18 and pin 44 of the device. by default, this pin functions as a power down input and the interrupt function is disabled. setting bit 0 (int_oe) of micr (11h) will configure the pin as an active low interrupt output. ports a and b can be powered down individually, using the separate pwrdown_int_a and pwrdown_int_b pins. copyright ? 2008 ? 2009, texas instruments incorporated design guidelines 63 submit documentation feedback product folder links: DP83849IF pin 31 (pfbout) pin 7 (pfbin1) pin 28 (pfbin2) pin34 (pfbin3) pin 54 (pfbin4) 0.1 p f 10 p f 0.1 p f 0.1 p f 0.1 p f 0.1 p f
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 7.6.1 power down control mode the pwrdown_int pins can be asserted low to put the device in a power down mode. this is equivalent to setting bit 11 (power down) in the basic mode control register, bmcr (00h). an external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. alternatively, the device can be configured to initialize into a power down state by use of an external pull-down resistor on the pwrdown_int pin. since the device will still respond to management register accesses, setting the int_oe bit in the micr register will disable the pwrdown_int input, allowing the device to exit the power down state. 7.6.2 interrupt mechanisms since each port has a separate interrupt pin, the interrupts can be connected individually or may be combined in a wired-or fashion. if the interrupts share a single connection, each port status should be checked following an interrupt. the interrupt function is controlled via register access. all interrupt sources are disabled by default. setting bit 1 (inten) of micr (11h) will enable interrupts to be output, dependent on the interrupt mask set in the lower byte of the misr (12h). the pwrdown_int pin is asynchronously asserted low when an interrupt condition occurs. the source of the interrupt can be determined by reading the upper byte of the misr. one or more bits in the misr will be set, denoting all currently pending interrupts. reading of the misr clears all pending interrupts. example: to generate an interrupt on a change of link status or on a change of energy detect power state, the steps would be: ? write 0003h to micr to set inten and int_oe ? write 0060h to misr to set ed_int_en and link_int_en ? monitor pwrdown_int pin when pwrdown_int pin asserts low, the user would read the misr register to see if the ed_int or link_int bits are set, i.e. which source caused the interrupt. after reading the misr, the interrupt bits should clear and the pwrdown_int pin will deassert. 7.7 energy detect mode when energy detect is enabled and there is no activity on the cable, the DP83849IF will remain in a low power mode while monitoring the transmission line. activity on the line will cause the DP83849IF to go through a normal power up sequence. regardless of cable activity, the DP83849IF will occasionally wake up the transmitter to put ed pulses on the line, but will otherwise draw as little power as possible. energy detect functionality is controlled via register energy detect control (edcr), address 1dh. 7.8 link diagnostic capabilities the DP83849IF contains several system diagnostic capabilities for evaluating link quality and detecting potential cabling faults in twisted pair cabling. software configuration is available through the link diagnostics registers - page 2 which can be selected via page select register (pagesel), address 13h. these capabilities include: ? linked cable status ? link quality monitor ? tdr (time domain reflectometry) cable diagnostics 64 design guidelines copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 7.8.1 linked cable status in an active connection with a valid link status, the following diagnostic capabilities are available: ? polarity reversal ? cable swap (mdi vs mdix) detection ? 100mb cable length estimation ? frequency offset relative to link partner ? cable signal quality estimation 7.8.1.1 polarity reversal the DP83849IF detects polarity reversal by detecting negative link pulses. the polarity indication is available in bit 12 of the physts (10h) or bit 4 of the 10btscr (1ah). inverted polarity indicates the positive and negative conductors in the receive pair are swapped. since polarity is corrected by the receiver, this does not necessarily indicate a functional problem in the cable. since the polarity indication is dependent on link pulses from the link partner, polarity indication is only valid in 10mb modes of operation, or in 100mb auto-negotiated mode. polarity indication is not available in 100mb forced mode of operation or in a parallel detected 100mb mode. 7.8.1.2 cable swap indication as part of auto-negotiation, the DP83849IF has the ability (using auto-mdix) to automatically detect a cable with swapped mdi pairs and select the appropriate pairs for transmitting and receiving data. normal operation is termed mdi, while crossed operation is mdix. the mdix status can be read from bit 14 of the physts (10h). 7.8.1.3 100mb cable length estimation the DP83849IF provides a method of estimating cable length based on electrical characteristics of the 100mb link. this essentially provides an effective cable length rather than a measurement of the physical cable length. the cable length estimation is only available in 100mb mode of operation with a valid link status. the cable length estimation is available at the link diagnostics registers - page 2, register 100mb length detect (len100_det), address 14h. 7.8.1.4 frequency offset relative to link partner as part of the 100mb clock recovery process, the dsp implementation provides a frequency control parameter. this value may be used to indicate the frequency offset of the device relative to the link partner. this operation is only available in 100mb operation with a valid link status. the frequency offset can be determined using the register 100mb frequency offset indication (freq100), address 15h, of the link diagnostics registers - page 2. two different versions of the frequency offset may be monitored through bits [7:0] of register freq100 (15h). the first is the long-term frequency offset. the second is the current frequency control value, which includes short-term phase adjustments and can provide information on the amount of jitter in the system. 7.8.1.5 cable signal quality estimation the cable signal quality estimator keeps a simple tracking of results of the dsp and can be used to generate an approximate signal-to-noise ratio for the 100mb receiver. this information is available to software through the link diagnostics registers - page 2: variance control (var_ctrl), address 1ah and data (var_data), address 1bh. the variance computation times (var_timer) can be chosen from the set of {2, 4, 6, 8} ms. the 32-bit variance sum can be read by two consecutive reads of the var_data register. this sum can be used to compute an snr estimate by software using the following equation: snr = 10log10((37748736 * var_timer) / variance). (1) copyright ? 2008 ? 2009, texas instruments incorporated design guidelines 65 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 7.8.2 link quality monitor the link quality monitor allows a method to generate an alarm when the dsp adaption strays from a programmable window. this could occur due to changes in the cable which could indicate a potential problem. software can program thresholds for the following dsp parameters to be used to interrupt the system: ? digital equalizer c1 coefficient (deq c1) ? digital adaptive gain control (dagc) ? digital base-line wander control (dblw) ? recovered clock long-term frequency offset (freq) ? recovered clock frequency control (fc) software is expected to read initial adapted values and then program the thresholds based on an expected valid range. this mechanism takes advantage of the fact that the dsp adaption should remain in a relatively small range once a valid link has been established. 7.8.2.1 link quality monitor control and status control of the link quality monitor is done through the link quality monitor register (lqmr), address 1dh and the link quality data register (lqdr), address 1bh of the link diagnostics registers - page 2. the lqmr register includes a global enable to enable the link quality monitor function. in addition, it provides warning status from both high and low thresholds for each of the monitored parameters. note that individual low or high parameter threshold comparisons can be disabled by setting to the minimum or maximum values. to allow the link quality monitor to interrupt the system, the interrupt must be enabled through the interrupt control registers, micr (11h) and misr (12h). 7.8.2.2 checking current parameter values prior to setting threshold values, it is recommended that software check current adapted values. the thresholds may then be set relative to the adapted values. the current adapted values can be read using the lqdr register by setting the sample_param bit [13] of lqdr, address (1eh). for example, to read the dblw current value: 1. write 2400h to lqdr (1eh) to set the sample_param bit and set the lq_param_sel[2:0] to 010. 2. read lqdr (1eh). current dblw value is returned in the low 8 bits. 7.8.2.3 threshold control the lqdr (1eh) register also provides a method of programming high and low thresholds for each of the four parameters that can be monitored. the register implements an indirect read/write mechanism. writes are accomplished by writing data, address, and a write strobe to the register. reads are accomplished by writing the address to the register, and reading back the value of the selected threshold. setting thresholds to the maximum or minimum values will disable the threshold comparison since values have to exceed the threshold to generate a warning condition. warnings are not generated if the parameter is equal to the threshold. by default, all thresholds are disabled by setting to the min or max values. the following table shows the four parameters and range of values: 66 design guidelines copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 7-4. link quality monitor parameter ranges parameter minimum value maximum value min (2-s comp) max (2-s comp) deq c1 -128 +127 0x80 0x7f dagc 0 +255 0x00 0xff dblw -128 +127 0x80 0x7f freq offset -128 +127 0x80 0x7f freq control -128 +127 0x80 0x7f 7.8.3 tdr cable diagnostics the DP83849IF implements a time domain reflectometry (tdr) method of cable length measurement and evaluation which can be used to evaluate a connected twisted pair cable. the tdr implementation involves sending a pulse out on either the transmit or receive conductor pair and observing the results on either pair. by observing the types and strength of reflections on each pair, software can determine the following: ? cable short ? cable open ? distance to fault ? identify which pair has a fault ? pair skew the tdr cable diagnostics works best in certain conditions. for example, an unterminated cable provides a good reflection for measuring cable length, while a cable with an ideal termination to an unpowered partner may provide no reflection at all. 7.8.4 tdr pulse generator the tdr implementation can send two types of tdr pulses. the first option is to send 50ns or 100ns link pulses from the 10mb common driver. the second option is to send pulses from the 100mb common driver in 8ns increments up to 56ns in width. the 100mb pulses will alternate between positive and negative pulses. the shorter pulses provide better ability to measure short cable lengths, especially since they will limit overlap between the transmitted pulse and a reflected pulse. the longer pulses may provide better measurements of long cable lengths. in addition, if the pulse width is programmed to 0, no pulse will be sent, but monitor circuit will still be activated. this allows sampling of background data to provide a baseline for analysis. 7.8.5 tdr pulse monitor the tdr function monitors data from the analog to digital converter (adc) to detect both peak values and values above a programmable threshold. it can be programmed to detect maximum or minimum values. in addition, it records the time, in 8ns intervals, at which the peak or threshold value first occurs. the tdr monitor implements a timer that starts when the pulse is transmitted. a window may be enabled to qualify incoming data to look for response only in a desired range. this is especially useful for eliminating the transmitted pulse, but also may be used to look for multiple reflections. 7.8.6 tdr control interface the tdr control interface is implemented in the link diagnostics registers - page 2 through tdr control (tdr_ctrl), address 16h and tdr window (tdr_win), address 17h. the following basic controls are: tdr enable: enable bit 15 of tdr_ctrl (16h) to allow the tdr function. this bypasses normal operation and gives control of the cd10 and cd100 block to the tdr function. tdr send pulse: enable bit 11 of tdr_ctrl (16h) to send the tdr pulse and starts the tdr monitor the following transmit mode controls are available: copyright ? 2008 ? 2009, texas instruments incorporated design guidelines 67 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com transmit mode: enables use of 10mb link pulses from the 10mb common driver or data pulses from the 100mb common driver by enabling tdr 100mb, bit 14 of tdr_crtl (16h). transmit pulse width: bits [10:8] of tdr_ctrl (16h) allows sending of 0 to 7 clock width pulses. actual pulses are dependent on the transmit mode. if pulse width is set to 0, then no pulse will be sent. transmit channel select: the transmitter can send pulses down either the transmit pair or the receive pair by enabling bit 13 of tdr_ctrl (16h). default value is to select the transmit pair. the following receive mode controls are available: min/max mode select: bit 7 of tdr_ctrl (16h) controls the tdr monitor operation. in default mode, the monitor will detect maximum (positive) values. in min mode, the monitor will detect minimum (negative) values. receive channel select: the receiver can monitor either the transmit pair or the receive pair by enabling bit 12 of tdr_ctrl (16h). default value is to select the transmit pair. receive window: the receiver can monitor receive data within a programmable window using the tdr window register (tdr_win), address 17h. the window is controlled by two register values: tdr start window, bits [15:8] of tdr_win (17h) and tdr stop window, bits [7:0] of tdr_win (17h). the tdr start window indicates the first clock to start sampling. the tdr stop window indicates the last clock to sample. by default, the full window is enabled, with start set to 0 and stop set to 255. the window range is in 8ns clock increments, so the maximum window size is 2048ns. 7.8.7 tdr results the tdr function monitors data from the analog to digital converter (adc) to detect both peak values and values above a programmable threshold. it can be programmed to detect maximum or minimum values. in addition, it records the time, in 8ns intervals, at which the peak or threshold value first occurs. the results of a tdr peak and threshold measurement are available in the tdr peak measurement register (tdr_peak), address 18h and tdr threshold measurement register (tdr_thr), address 19h. the threshold measurement may be a more accurate method of measuring the length for longer cables to provide a better indication of the start of the received pulse, rather than the peak value. software utilizing the tdr function should implement an algorithm to send tdr pulses and evaluate results. multiple runs should be used to best qualify any received pulses as multiple reflections could exist. in addition, when monitoring the transmitting pair, the window feature should be used to disqualify the transmitted pulse. multiple runs may also be used to average the values providing more accurate results. actual distance measurements are dependent on the velocity of propagation of the cable. the delay value is typically on the order of 4.6 to 4.9 ns/m. 68 design guidelines copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 8 reset operation the DP83849IF includes an internal power-on reset (por) function and does not need to be explicitly reset for normal operation after power up. if required during normal operation, the device can be reset by a hardware or software reset. 8.1 hardware reset a hardware reset is accomplished by applying a low pulse (ttl level), with a duration of at least 1 ms, to the reset_n pin. this will reset the device such that all registers will be reinitialized to default values and the hardware configuration values will be re-latched into the device (similar to the power-up/reset operation). 8.2 full software reset a full-chip software reset is accomplished by setting the reset bit (bit 15) of the basic mode control register (bmcr). the period from the point in time when the reset bit is set to the point in time when software reset has concluded is approximately 1 s. the software reset will reset the device such that all registers will be reset to default values and the hardware configuration values will be maintained. software driver code must wait 3 ms following a software reset before allowing further serial mii operations with the DP83849IF. 8.3 soft reset a partial software reset can be initiated by setting the soft reset bit (bit 9) in the phycr2 register. setting this bit will reset all transmit and receive operations, but will not reset the register space. all register configurations will be preserved. register space will remain available following a soft reset. copyright ? 2008 ? 2009, texas instruments incorporated reset operation 69 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9 register block table 9-1. register map offset access tag description hex decimal 00h 0 rw bmcr basic mode control register 01h 1 ro bmsr basic mode status register 02h 2 ro phyidr1 phy identifier register #1 03h 3 ro phyidr2 phy identifier register #2 04h 4 rw anar auto-negotiation advertisement register 05h 5 rw anlpar auto-negotiation link partner ability register (base page) 05h 5 rw anlparnp auto-negotiation link partner ability register (next page) 06h 6 rw aner auto-negotiation expansion register 07h 7 rw annptr auto-negotiation next page tx 08h-fh 8-15 reserved reserved 10h 16 ro physts phy status register 11h 17 rw micr mii interrupt control register 12h 18 rw misr mii interrupt status register 13h 19 rw pagesel page select register extended registers - page 0 14h 20 ro fcscr false carrier sense counter register 15h 21 ro recr receive error counter register 16h 22 rw pcsr pcs sub-layer configuration and status register 17h 23 rw rbr rmii and bypass register 18h 24 rw ledcr led direct control register 19h 25 rw phycr phy control register 1ah 26 rw 10btscr 10base-t status/control register 1bh 27 rw cdctrl1 cd test control register and bist extensions register 1ch 28 rw phycr2 phy control register 2 1dh 29 rw edcr energy detect control register 1eh-1fh 30-31 reserved reserved reserved registers 14h-1fh 20-31 reserved reserved link diagnostics registers - page 2 14h 20 ro len100_det 100mb length detect register 15h 21 rw freq100 100mb frequency offset indication register 16h 22 rw tdr_ctrl tdr control register 17h 23 rw tdr_win tdr window register 18h 24 ro tdr_peak tdr peak measurement register 19h 25 ro tdr_thr tdr threshold measurement register 1ah 26 rw var_ctrl variance control register 1bh 27 ro var_dat variance data register 1ch 28 reserved reserved 1dh 29 rw lqmr link quality monitor register 1eh 30 rw lqdr link quality data register 1fh 31 reserved reserved 70 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 9-2. register table register name addr tag bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 basic mode 00h bmcr reset loopback speed auto-neg power isolate restart duplex collision reserved reserved reserved reserved reserved reserved reserved control register selection enable down auto-neg mode test basic mode status 01h bmsr 100base- 100base- 100base- 10base-t 10base-t reserved reserved reserved reserved mf auto-neg remote auto-neg link jabber detect extended register t4 tx fdx tx hdx preamble fault capability fdx hdx complete ability status suppress phy identifier 02h phyidr1 oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb oui msb register 1 phy identifier 03h phyidr2 oui lsb oui lsb oui lsb oui lsb oui lsb oui lsb vndr_ vndr_ vndr_ vndr_ vndr_ vndr_ mdl_ mdl_ mdl_ mdl_ register 2 mdl mdl mdl mdl mdl mdl rev rev rev rev auto-negotiation 04h anar next page reserved remote reserved asm_dir pause t4 tx_fd tx 10_fd 10 protocol protocol protocol protocol protocol advertisement ind fault selection selection selection selection selection register auto-negotiation 05h anlpar next page ack remote reserved asm_dir pause t4 tx_fd tx 10_fd 10 protocol protocol protocol protocol protocol link partner ability ind fault selection selection selection selection selection register (base page) auto-negotiation 05h anlparn next page ack message ack2 toggle code code code code code code code code code code code link partner ability p ind page register next page auto-negotiation 06h aner reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved pdf lp_np_ np_ page_ lp_an_ expansion able able rx able register auto-negotiation 07h annptr next page reserved message ack2 tog_tx code code code code code code code code code code code next page tx ind page register reserved 08-0fh reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved phy status 10h physts reserved mdix rx err polarity false signal descrambl page mii remote jabber detect auto-neg loopback duplex speed status link register mode latch status carrier detect er lock interrupt fault status status receive complete status sense mii interrupt 11h micr reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved tint inten int_oe control register mii interrupt status 12h misr lq_int ed_int link_int spd_int dup_int anc_int fhf_int rhf_int lq_int_e ed_int_e link_int_en sped_int dup_int_en anc_int_ fhf_int_en rhf_int_ and misc. control n n _en en en register page select 13h reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved page_sel bit page_sel register bit extended registers - page 0 false carrier 14h fcscr reserved reserved reserved reserved reserved reserved reserved reserved fcscnt fcscnt fcscnt fcscnt fcscnt fcscnt fcscnt fcscnt sense counter register receive error 15h recr reserved reserved reserved reserved reserved reserved reserved reserved rxercnt rxercnt rxercnt rxercnt rxercnt rxercnt rxercnt rxercnt counter register pcs sub-layer 16h pcsr reserved reserved reserved reserved free_clk tq_en sd_forc sd_ desc_tim fx_en force_ reserved fefi_en nrzi_ scram_ de configuration and e_pma e option 100_ok bypass bypass scram_b status register ypass rmii and bypass 17h rbr sim_writ reserved dis_tx_o rx_port rx_port tx_sour tx_sour pmd_loo scmii_rx scmii_tx rmii_mode rmii_rev rx_ovf_st rx_unf_s elast_buf elast_bu register e pt ce ce p 1_0 s ts f copyright ? 2008 ? 2009, texas instruments incorporated register block 71 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com table 9-2. register table (continued) register name addr tag bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 led direct control 18h ledcr reserved reserved reserved reserved reserved reserved reserved ledact_r blink_fr blink_fr drv_spdle drv_lnkl drv_actle spdled lnkled actled register x eq eq d ed d phy control 19h phycr mdix_en force_m pause_r pause_tx bist_fe psr_15 bist_ bist_sta bp_stret led_ led_ phy phy phy phy phy register dix x rt ch status cnfg[1] cnfg[0] addr addr addr addr addr 10base-t 1ah 10bt_ser reserved reserved reserved reserved squelch squelch squelch loopbac lp_dis force_ reserved polarity reserved reserved heartbeat jabber_d status/control ial k_10_dis _dis is link_10 register cd test control 1bh cdctrl1 bist_err bist_err bist_err bist_err bist_err bist_err bist_err bist_err reserved reserved bist_cont_ cdpatten_ reserved 10meg_pat cdpattsel cdpattsel and bist or_coun or_coun or_coun or_coun or_coun or_coun or_coun or_coun mode 10 t_gap extensions t t t t t t t t register phy control 1ch phycr2 reserved reserved reserved reserved reserved reserved soft_re reserved reserved reserved reserved reserved reserved reserved reserved reserved register 2 set energy detect 1dh edcr ed_en ed_auto ed_auto ed_man ed_burs ed_pwr_ ed_err_ ed_data_ ed_err_ ed_err_ ed_err_co ed_err_ ed_data_c ed_data_ ed_data_c ed_data_ control register _up _down t_dis state met met count count unt count ount count ount count reserved 1eh-1fh reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved registers reserved 14h-1fh reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved link diagnostics registers - page 2 100mb length 14h len100_d reserved reserved reserved reserved reserved reserved reserved reserved cable_le cable_le cable_len cable_le cable_len cable_le cable_len cable_le detect register et n n n n n 100mb frequency 15h freq100 sample_f reserved reserved reserved reserved reserved reserved sel_fc freq_of freq_of freq_offs freq_of freq_offs freq_of freq_offs freq_of offset indication req fset fset et fset et fset et fset register tdr control 16h tdr_ctrl tdr_ena tdr_100m tx_chan rx_chan send_td tdr_widt tdr_widt tdr_widt tdr_min_ reserved rx_thresh rx_thre rx_thresh rx_thre rx_thresh rx_thre register ble b nel nel r h h h mode old shold old shold old shold tdr window 17h tdr_win tdr_sta tdr_sta tdr_sta tdr_sta tdr_sta tdr_sta tdr_sta tdr_sta tdr_sto tdr_sto tdr_stop tdr_sto tdr_stop tdr_sto tdr_stop tdr_sto register rt rt rt rt rt rt rt rt p p p p p tdr peak 18h tdr_pea reserved reserved tdr_pea tdr_pea tdr_pea tdr_pea tdr_pea tdr_pea tdr_pea tdr_pea tdr_peak_ tdr_pea tdr_peak_ tdr_pea tdr_peak_ tdr_pea register k k k k k k k k_time k_time time k_time time k_time time k_time tdr threshold 19h tdr_thr reserved reserved reserved reserved reserved reserved reserved tdr_thr_ tdr- tdr- tdr- tdr- tdr- tdr- tdr- tdr- register met thr_time thr_time thr_time thr_time thr_time thr_time thr_time thr_time variance control 1ah var_ctrl var_rdy reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved var_freez var_time var_timer var_time register e r r variance data 1bh var_dat var_dat var_dat var_dat var_dat var_dat var_dat var_dat var_dat var_dat var_dat var_data var_dat var_data var_dat var_data var_dat register a a a a a a a a a a a a a a reserved 1ch reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved link quality 1dh lqmr lqm_ena reserved reserved reserved reserved reserved fc_hi_wa fc_lo_w freq_hi_ freq_lo_ dblw_hi_w dblw_lo dagc_hi_w dagc_lo c1_hi_war c1_lo_w monitor register ble rn arn warn warn arn _warn arn _warn n arn link quality data 1eh lqdr reserved reserved sample_ write_lq lq_para lq_para lq_para lq_thr_s lq_thr_d lq_thr_d lq_thr_da lq_thr_d lq_thr_da lq_thr_d lq_thr_da lq_thr_d register param _thr m_sel m_sel m_sel el ata ata ta ata ta ata ta ata reserved 1fh reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 72 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.1 register definition in the register definitions under the ? default ? heading, the following definitions hold true: rw = r ead w rite access sc = register sets on event occurrence and s elf- c lears when event ends rw/sc = r ead w rite access/ s elf c learing bit ro = r ead o nly access cor = c lear o n r ead ro/cor = r ead o nly, c lear o n r ead ro/p = r ead o nly, p ermanently set to a default value ll = l atched l ow and held until read, based upon the occurrence of the corresponding event lh = l atched h igh and held until read, based upon the occurrence of the corresponding event copyright ? 2008 ? 2009, texas instruments incorporated register block 73 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.1.1 basic mode control register (bmcr) table 9-3. basic mode control register (bmcr), address 00h bit bit name default description 15 reset 0, rw/sc reset: 1 = initiate software reset / reset in process. 0 = normal operation. this bit, which is self-clearing, returns a value of one until the reset process is complete. the configuration is re-strapped. 14 loopback 0, rw loopback: 1 = loopback enabled. 0 = normal operation. the loopback function enables mii transmit data to be routed to the mii receive data path. setting this bit may cause the descrambler to lose synchronization and produce a 500 s ? dead time ? before any valid data will appear at the mii receive outputs. 13 speed strap, rw speed select: selection when auto-negotiation is disabled writing to this bit allows the port speed to be selected. 1 = 100 mb/s. 0 = 10 mb/s. 12 auto- strap, rw auto-negotiation enable: negotiation strap controls initial value at reset. enable if fx is enabled (fx_en = 1), then this bit will be reset to 0. 1 = auto-negotiation enabled - bits 8 and 13 of this register are ignored when this bit is set. 0 = auto-negotiation disabled - bits 8 and 13 determine the port speed and duplex mode. 11 power down 0, rw power down: 1 = power down. 0 = normal operation. setting this bit powers down the phy. only the register block is enabled during a power down condition. this bit is ord with the input from the pwrdown_int pin. when the active low pwrdown_int pin is asserted, this bit will be set. 10 isolate 0, rw isolate: 1 = isolates the port from the mii with the exception of the serial management. 0 = normal operation. 9 restart 0, rw/sc restart auto-negotiation: auto- 1 = restart auto-negotiation. re-initiates the auto-negotiation process. if auto-negotiation is negotiation disabled (bit 12 = 0), this bit is ignored. this bit is self-clearing and will return a value of 1 until auto-negotiation is initiated, whereupon it will self-clear. operation of the auto-negotiation process is not affected by the management entity clearing this bit. 0 = normal operation. 8 duplex mode strap, rw duplex mode: when auto-negotiation is disabled writing to this bit allows the port duplex capability to be selected. 1 = full duplex operation. 0 = half duplex operation. 7 collision 0, rw collision test: test 1 = collision test enabled. 0 = normal operation. when set, this bit will cause the col signal to be asserted in response to the assertion of tx_en within 512-bit times. the col signal will be de-asserted within 4-bit times in response to the de- assertion of tx_en. 6:0 reserved 0, ro reserved: write ignored, read as 0. 74 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.1.2 basic mode status register (bmsr) table 9-4. basic mode status register (bmsr), address 01h bit bit name default description 15 100base-t4 0, ro/p 100base-t4 capable: 0 = device not able to perform 100base-t4 mode. 14 100base-tx 1, ro/p 100base-tx full duplex capable: full duplex 1 = device able to perform 100base-tx in full duplex mode. 13 100base-tx 1, ro/p 100base-tx half duplex capable: half duplex 1 = device able to perform 100base-tx in half duplex mode. 12 10base-t 1, ro/p 10base-t full duplex capable: full duplex 1 = device able to perform 10base-t in full duplex mode. 11 10base-t 1, ro/p 10base-t half duplex capable: half duplex 1 = device able to perform 10base-t in half duplex mode. 10:7 reserved 0, ro reserved : write as 0, read as 0. 6 mf preamble 1, ro/p preamble suppression capable: suppression 1 = device able to perform management transaction with preamble suppressed, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround. 0 = normal management operation. 5 auto-negotiation 0, ro auto-negotiation complete: complete 1 = auto-negotiation process complete. 0 = auto-negotiation process not complete. 4 remote fault 0, ro/lh remote fault: 1 = remote fault condition detected (cleared on read or by reset). fault criteria: far end fault indication or notification from link partner of remote fault. 0 = no remote fault condition detected. 3 auto-negotiation 1, ro/p auto negotiation ability: ability 1 = device is able to perform auto-negotiation. 0 = device is not able to perform auto-negotiation. 2 link status 0, ro/ll link status: 1 = valid link established (for either 10 or 100 mb/s operation). 0 = link not established. the criteria for link validity is implementation specific. the occurrence of a link failure condition will causes the link status bit to clear. once cleared, this bit may only be set by establishing a good link condition and a read via the management interface. 1 jabber detect 0, ro/lh jabber detect: this bit only has meaning in 10 mb/s mode. 1 = jabber condition detected. 0 = no jabber. this bit is implemented with a latching function, such that the occurrence of a jabber condition causes it to set until it is cleared by a read to this register by the management interface or by a reset. 0 extended capability 1, ro/p extended capability: 1 = extended register capabilities. 0 = basic register set capabilities only. copyright ? 2008 ? 2009, texas instruments incorporated register block 75 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com the phy identifier registers #1 and #2 together form a unique identifier for the DP83849IF. the identifier consists of a concatenation of the organizationally unique identifier (oui), the vendor's model number and the model revision number. a phy may return a value of zero in each of the 32 bits of the phy identifier if desired. the phy identifier is intended to support network management. ti's ieee assigned oui is 080017h. 9.1.3 phy identifier register #1 (phyidr1) table 9-5. phy identifier register #1 (phyidr1), address 02h bit bit name default description 15:0 oui_msb < 0010 0000 0000 oui most significant bits: bits 3 to 18 of the oui (080017h) are stored in bits 15 0000 > , ro/p to 0 of this register. the most significant two bits of the oui are ignored (the ieee standard refers to these as bits 1 and 2). 9.1.4 phy identifier register #2 (phyidr2) table 9-6. phy identifier register #2 (phyidr2), address 03h bit bit name default description 15:10 oui_lsb < 0101 11 > , ro/p oui least significant bits: bits 19 to 24 of the oui (080017h) are mapped from bits 15 to 10 of this register respectively. 9:4 vndr_mdl < 00 1010 > , ro/p vendor model number: the six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9). 3:0 mdl_rev < 0010 > , ro/p model revision number: four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant bit to bit 3). this field will be incremented for all major device changes. 76 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.1.5 auto-negotiation advertisement register (anar) this register contains the advertised abilities of this device as they will be transmitted to its link partner during auto-negotiation. any writes to this register prior to completion of auto-negotiation (as indicated in the basic mode status register (address 01h) auto-negotiation complete bit, bmsr[5]) should be followed by a renegotiation. this will ensure that the new values are properly used in the auto-negotiation. table 9-7. negotiation advertisement register (anar), address 04h bit bit name default description 15 np 0, rw next page indication: 0 = next page transfer not desired. 1 = next page transfer desired. 14 reserved 0, ro/p reserved by ieee : writes ignored, read as 0. 13 rf 0, rw remote fault: 1 = advertises that this device has detected a remote fault. 0 = no remote fault detected. 12 reserved 0, rw reserved for future ieee use: write as 0, read as 0 11 asm_dir 0, rw asymmetric pause support for full duplex links: the asm_dir bit indicates that asymmetric pause is supported. encoding and resolution of pause bits is defined in ieee 802.3 annex 28b, tables 28b-2 and 28b-3, respectively. pause resolution status is reported in phycr[13:12]. 1 = advertise that the dte (mac) has implemented both the optional mac control sublayer and the pause function as specified in clause 31 and annex 31b of 802.3u. 0= no mac based full duplex flow control. 10 pause 0, rw pause support for full duplex links: the pause bit indicates that the device is capable of providing the symmetric pause functions as defined in annex 31b. encoding and resolution of pause bits is defined in ieee 802.3 annex 28b, tables 28b-2 and 28b-3, respectively. pause resolution status is reported in phycr[13:12]. 1 = advertise that the dte (mac) has implemented both the optional mac control sublayer and the pause function as specified in clause 31 and annex 31b of 802.3u. 0= no mac based full duplex flow control. 9 t4 0, ro/p 100base-t4 support: 1= 100base-t4 is supported by the local device. 0 = 100base-t4 not supported. 8 tx_fd strap, rw 100base-tx full duplex support: 1 = 100base-tx full duplex is supported by the local device. 0 = 100base-tx full duplex not supported. 7 tx strap, rw 100base-tx support: 1 = 100base-tx is supported by the local device. 0 = 100base-tx not supported. 6 10_fd strap, rw 10base-t full duplex support: 1 = 10base-t full duplex is supported by the local device. 0 = 10base-t full duplex not supported. 5 10 strap, rw 10base-t support: 1 = 10base-t is supported by the local device. 0 = 10base-t not supported. 4:0 selector < 00001 > , rw protocol selection bits: these bits contain the binary encoded protocol selector supported by this port. < 00001 > indicates that this device supports ieee 802.3u. copyright ? 2008 ? 2009, texas instruments incorporated register block 77 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.1.6 auto-negotiation link partner ability register (anlpar) (base page) this register contains the advertised abilities of the link partner as received during auto-negotiation. the content changes after the successful auto-negotiation if next-pages are supported. table 9-8. auto-negotiation link partner ability register (anlpar) (base page), address 05h bit bit name default description 15 np 0, ro next page indication: 0 = link partner does not desire next page transfer. 1 = link partner desires next page transfer. 14 ack 0, ro acknowledge : 1 = link partner acknowledges reception of the ability data word. 0 = not acknowledged. the auto-negotiation state machine will automatically control the this bit based on the incoming flp bursts. 13 rf 0, ro remote fault: 1 = remote fault indicated by link partner. 0 = no remote fault indicated by link partner. 12 reserved 0, ro reserved for future ieee use: write as 0, read as 0. 11 asm_dir 0, ro asymmetric pause: 1 = asymmetric pause is supported by the link partner. 0 = asymmetric pause is not supported by the link partner. 10 pause 0, ro pause: 1 = pause function is supported by the link partner. 0 = pause function is not supported by the link partner. 9 t4 0, ro 100base-t4 support: 1 = 100base-t4 is supported by the link partner. 0 = 100base-t4 not supported by the link partner. 8 tx_fd 0, ro 100base-tx full duplex support: 1 = 100base-tx full duplex is supported by the link partner. 0 = 100base-tx full duplex not supported by the link partner. 7 tx 0, ro 100base-tx support: 1 = 100base-tx is supported by the link partner. 0 = 100base-tx not supported by the link partner. 6 10_fd 0, ro 10base-t full duplex support: 1 = 10base-t full duplex is supported by the link partner. 0 = 10base-t full duplex not supported by the link partner. 5 10 0, ro 10base-t support: 1 = 10base-t is supported by the link partner. 0 = 10base-t not supported by the link partner. 4:0 selector < 0 0000 > , ro protocol selection bits: link partners binary encoded protocol selector. 78 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.1.7 auto-negotiation link partner ability register (anlpar) (next page) table 9-9. auto-negotiation link partner ability register (anlpar) (next page), address 05h bit bit name default description 15 np 0, ro next page indication: 1 = link partner desires next page transfer. 0 = link partner does not desire next page transfer. 14 ack 0, ro acknowledge: 1 = link partner acknowledges reception of the ability data word. 0 = not acknowledged. the auto-negotiation state machine will automatically control the this bit based on the incoming flp bursts. software should not attempt to write to this bit. 13 mp 0, ro message page: 1 = message page. 0 = unformatted page. 12 ack2 0, ro acknowledge 2: 1 = link partner does have the ability to comply to next page message. 0 = link partner does not have the ability to comply to next page message. 11 toggle 0, ro toggle: 1 = previous value of the transmitted link code word equalled 0. 0 = previous value of the transmitted link code word equalled 1. 10:0 code < 000 0000 0000 > , code: ro this field represents the code field of the next page transmission. if the mp bit is set (bit 13 of this register), then the code shall be interpreted as a message page, as defined in annex 28c of clause 28. otherwise, the code shall be interpreted as an unformatted page, and the interpretation is application specific. 9.1.8 auto-negotiate expansion register (aner) this register contains additional local device and link partner status information. table 9-10. auto-negotiate expansion register (aner), address 06h bit bit name default description 15:5 reserved 0, ro reserved : writes ignored, read as 0. 4 pdf 0, ro parallel detection fault: 1 = a fault has been detected via the parallel detection function. 0 = a fault has not been detected. 3 lp_np_able 0, ro link partner next page able: 1 = link partner does support next page. 0 = link partner does not support next page. 2 np_able 1, ro/p next page able: 1 = indicates local device is able to send additional next pages. 1 page_rx 0, ro/cor link code word page received: 1 = link code word has been received, cleared on a read. 0 = link code word has not been received. 0 lp_an_able 0, ro link partner auto-negotiation able: 1 = indicates that the link partner supports auto-negotiation. 0 = indicates that the link partner does not support auto-negotiation. copyright ? 2008 ? 2009, texas instruments incorporated register block 79 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.1.9 auto-negotiation next page transmit register (annptr) this register contains the next page information sent by this device to its link partner during auto- negotiation. table 9-11. auto-negotiation next page transmit register (annptr), address 07h bit bit name default description 15 np 0, rw next page indication: 0 = no other next page transfer desired. 1 = another next page desired. 14 reserved 0, ro reserved: writes ignored, read as 0. 13 mp 1, rw message page: 1 = message page. 0 = unformatted page. 12 ack2 0, rw acknowledge2: 1 = will comply with message. 0 = cannot comply with message. acknowledge2 is used by the next page function to indicate that local device has the ability to comply with the message received. 11 tog_tx 0, ro toggle: 1 = value of toggle bit in previously transmitted link code word was 0. 0 = value of toggle bit in previously transmitted link code word was 1. toggle is used by the arbitration function within auto-negotiation to ensure synchronization with the link partner during next page exchange. this bit shall always take the opposite value of the toggle bit in the previously exchanged link code word. 10:0 code < 000 0000 0001 > , rw code: this field represents the code field of the next page transmission. if the mp bit is set (bit 13 of this register), then the code shall be interpreted as a "message page ? , as defined in annex 28c of ieee 802.3u. otherwise, the code shall be interpreted as an "unformatted page ? , and the interpretation is application specific. the default value of the code represents a null page as defined in annex 28c of ieee 802.3u. 80 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.1.10 phy status register (physts) this register provides a single location within the register set for quick access to commonly accessed information. table 9-12. phy status register (physts), address 10h bit bit name default description 15 reserved 0, ro reserved: write ignored, read as 0. 14 mdix mode 0, ro mdix mode as reported by the auto-negotiation logic: this bit will be affected by the settings of the mdix_en and force_mdix bits in the phycr register. when mdix is enabled, but not forced, this bit will update dynamically as the auto-mdix algorithm swaps between mdi and mdix configurations. 1 = mdi pairs swapped (receive on tptd pair, transmit on tprd pair) 0 = mdi pairs normal (receive on trd pair, transmit on tptd pair) 13 receive error 0, ro/lh receive error latch: latch this bit will be cleared upon a read of the recr register. 1 = receive error event has occurred since last read of rxercnt (address 15h, page 0). 0 = no receive error event has occurred. 12 polarity status 0, ro polarity status: this bit is a duplication of bit 4 in the 10btscr register. this bit will be cleared upon a read of the 10btscr register, but not upon a read of the physts register. 1 = inverted polarity detected. 0 = correct polarity detected. 11 false carrier sense 0, ro/lh false carrier sense latch: latch this bit will be cleared upon a read of the fcsr register. 1 = false carrier event has occurred since last read of fcscr (address 14h). 0 = no false carrier event has occurred. 10 signal detect 0, ro/ll 100base-tx qualified signal detect from pma: this is the sd that goes into the link monitor. it is the and of raw sd and descrambler lock, when address 16h, bit 8 (page 0) is set. when this bit is cleared, it will be equivalent to the raw sd from the pmd. 9 descrambler lock 0, ro/ll 100base-tx descrambler lock from pmd. 8 page received 0, ro link code word page received: this is a duplicate of the page received bit in the aner register, but this bit will not be cleared upon a read of the physts register. 1 = a new link code word page has been received. cleared on read of the aner (address 06h, bit 1). 0 = link code word page has not been received. 7 mii interrupt 0, ro mii interrupt pending: 1 = indicates that an internal interrupt is pending. interrupt source can be determined by reading the misr register (12h). reading the misr will clear the interrupt. 0 = no interrupt pending. 6 remote fault 0, ro remote fault: 1 = remote fault condition detected (cleared on read of bmsr (address 01h) register or by reset). fault criteria: notification from link partner of remote fault via auto-negotiation. 0 = no remote fault condition detected. copyright ? 2008 ? 2009, texas instruments incorporated register block 81 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com table 9-12. phy status register (physts), address 10h (continued) bit bit name default description 5 jabber detect 0, ro jabber detect: this bit only has meaning in 10 mb/s mode. this bit is a duplicate of the jabber detect bit in the bmsr register, except that it is not cleared upon a read of the physts register. 1 = jabber condition detected. 0 = no jabber. 4 auto-neg complete 0, ro auto-negotiation complete: 1 = auto-negotiation complete. 0 = auto-negotiation not complete. 3 loopback status 0, ro loopback: 1 = loopback enabled. 0 = normal operation. 2 duplex status 0, ro duplex: this bit indicates duplex status and is determined from auto-negotiation or forced modes (1) . 1 = full duplex mode. 0 = half duplex mode. 1 speed status 0, ro speed10: this bit indicates the status of the speed and is determined from auto- negotiation or forced modes (1) . 1 = 10 mb/s mode. 0 = 100 mb/s mode. 0 link status 0, ro link status: this bit is a duplicate of the link status bit in the bmsr register, except that it will not be cleared upon a read of the physts register. 1 = valid link established (for either 10 or 100 mb/s operation). 0 = link not established. (1) this bit is only valid if auto-negotiation is enabled and complete and there is a valid link or if auto-negotiation is disabled and there is a valid link. 9.1.11 mii interrupt control register (micr) this register implements the mii interrupt phy specific control register. sources for interrupt generation include: energy detect state change, link state change, speed status change, duplex status change, auto-negotiation complete or any of the counters becoming half-full. the individual interrupt events must be enabled by setting bits in the mii interrupt status and event control register (misr). table 9-13. mii interrupt control register (micr), address 11h bit bit name default description 15:3 reserved 0, ro reserved: writes ignored, read as 0. 2 tint 0, rw test interrupt: forces the phy to generate an interrupt to facilitate interrupt testing. interrupts will continue to be generated as long as this bit remains set. 1 = generate an interrupt. 0 = do not generate interrupt. 1 inten 0, rw interrupt enable: enable interrupt dependent on the event enables in the misr register. 1 = enable event based interrupts. 0 = disable event based interrupts. 0 int_oe 0, rw interrupt output enable: enable interrupt events to signal via the pwrdown_int pin by configuring the pwrdown_int pin as an output. 1 = pwrdown_int is an interrupt output. 0 = pwrdown_int is a power down input. 82 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.1.12 mii interrupt status and misc. control register (misr) this register contains event status and enables for the interrupt function. if an event has occurred since the last read of this register, the corresponding status bit will be set. if the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. the micr register controls must also be set to allow interrupts. the status indications in this register will be set even if the interrupt is not enabled. table 9-14. mii interrupt status and misc. control register (misr), address 12h bit bit name default description 15 lq_int 0, ro/cor link quality interrupt: 1 = link quality interrupt is pending and is cleared by the current read. 0 = no link quality interrupt pending. 14 ed_int 0, ro/cor energy detect interrupt: 1 = energy detect interrupt is pending and is cleared by the current read. 0 = no energy detect interrupt pending. 13 link_int 0, ro/cor change of link status interrupt: 1 = change of link status interrupt is pending and is cleared by the current read. 0 = no change of link status interrupt pending. 12 spd_int 0, ro/cor change of speed status interrupt: 1 = speed status change interrupt is pending and is cleared by the current read. 0 = no speed status change interrupt pending. 11 dup_int 0, ro/cor change of duplex status interrupt: 1 = duplex status change interrupt is pending and is cleared by the current read. 0 = no duplex status change interrupt pending. 10 anc_int 0, ro/cor auto-negotiation complete interrupt: 1 = auto-negotiation complete interrupt is pending and is cleared by the current read. 0 = no auto-negotiation complete interrupt pending. 9 fhf_int 0, ro/cor false carrier counter half-full interrupt: 1 = false carrier counter half-full interrupt is pending and is cleared by the current read. 0 = no false carrier counter half-full interrupt pending. 8 rhf_int 0, ro/cor receive error counter half-full interrupt: 1 = receive error counter half-full interrupt is pending and is cleared by the current read. 0 = no receive error carrier counter half-full interrupt pending. 7 lq_int_en 0, rw enable interrupt on link quality monitor event. 6 ed_int_en 0, rw enable interrupt on energy detect event. 5 link_int_en 0, rw enable interrupt on change of link status. 4 spd_int_en 0, rw enable interrupt on change of speed status. 3 dup_int_en 0, rw enable interrupt on change of duplex status. 2 anc_int_en 0, rw enable interrupt on auto-negotiation complete event. 1 fhf_int_en 0, rw enable interrupt on false carrier counter register half-full event. 0 rhf_int_en 0, rw enable interrupt on receive error counter register half-full event. copyright ? 2008 ? 2009, texas instruments incorporated register block 83 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.1.13 page select register (pagesel) this register is used to enable access to the link diagnostics registers. table 9-15. page select register (pagesel), address 13h bit bit name default description 15:2 reserved 0, ro reserved : writes ignored, read as 0 1:0 page_sel 0, rw page_sel bit: selects between paged registers for address 14h to 1fh. 0 = extended registers page 0 1 = reserved 2 = link diagnostics registers page 2 9.2 extended registers - page 0 9.2.1 false carrier sense counter register (fcscr) this counter provides information required to implement the ? false carriers ? attribute within the mau managed object class of clause 30 of the ieee 802.3u specification. table 9-16. false carrier sense counter register (fcscr), address 14h bit bit name default description 15:8 reserved 0, ro reserved: writes ignored, read as 0 7:0 fcscnt[7:0] 0, ro/cor false carrier event counter: this 8-bit counter increments on every false carrier event. this counter sticks when it reaches its max count (ffh). 9.2.2 receiver error counter register (recr) this counter provides information required to implement the ? symbol error during carrier ? attribute within the phy managed object class of clause 30 of the ieee 802.3u specification. table 9-17. receiver error counter register (recr), address 15h bit bit name default description 15:8 reserved 0, ro reserved : writes ignored, read as 0. 7:0 rxercnt[7:0] 0, ro/cor rx_er counter: when a valid carrier is present and there is at least one occurrence of an invalid data symbol, this 8-bit counter increments for each receive error detected. this event can increment only once per valid carrier event. if a collision is present, the attribute will not increment. the counter sticks when it reaches its max count. 84 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.2.3 100 mb/s pcs configuration and status register (pcsr) this register contains control and status information for the 100base physical coding sublayer. table 9-18. 100 mb/s pcs configuration and status register (pcsr), address 16h bit bit name default description 15:12 reserved < 00 > , ro reserved: writes ignored, read as 0. 11 free_clk 0, rw receive clock: 1 = rx_clk is free-running. 0 = rx_clk phase adjusted based on alignment. 10 tq_en 0, rw 100mbs true quiet mode enable: 1 = transmit true quiet mode. 0 = normal transmit mode. 9 sd force pma 0, rw signal detect force pma: 1 = forces signal detection in pma. 0 = normal sd operation. 8 sd_option 1, rw signal detect option: 1 = default operation. link will be asserted following detection of valid signal level and descrambler lock. link will be maintained as long as signal level is valid. a loss of descrambler lock will not cause link status to drop. 0 = modified signal detect algorithm. link will be asserted following detection of valid signal level and descrambler lock. link will be maintained as long as signal level is valid and descrambler remains locked. 7 desc_time 0, rw descrambler timeout: increase the descrambler timeout. when set this should allow the device to receive larger packets ( > 9k bytes) without loss of synchronization. 1 = 2ms. 0 = 722us (per ansi x3.263: 1995 (tp-pmd) 7.2.3.3e). 6 fx_en strap, rw fx fiber mode enable: this bit is set when the fx_en strap option is selected (pulled high) for the respective port. 1 = enables fx operation. 0 = disables fx operation. 5 force_100_ok 0, rw force 100 mb/s good link: 1 = forces 100 mb/s good link. 0 = normal 100 mb/s operation. 4 reserved 0, ro reserved: writes ignored, read as 0. 3 fefi_en strap, rw far end fault indication mode enable: this bit is set when the fx_en strap option is selected for the respective port. 1 = fefi mode enabled. 0 = fefi mode disabled. 2 nrzi_bypass 0, rw nrzi bypass enable: 1 = nrzi bypass enabled. 0 = nrzi bypass disabled. 1 scram strap, rw scrambler bypass enable: bypass this bit is set when the fx_en strap option is selected for the respective port. in the fx mode, the scrambler is bypassed. 1 = scrambler bypass enabled. 0 = scrambler bypass disabled. 0 descram strap, rw descrambler bypass enable: bypass this bit is set when the fx_en strap option is selected for the respective port. in the fx mode, the descrambler is bypassed. 1 = descrambler bypass enabled. 0 = descrambler bypass disabled. copyright ? 2008 ? 2009, texas instruments incorporated register block 85 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.2.4 rmii and bypass register (rbr) this register configures the rmii/mii interface mode of operation. this register controls selecting mii, rmii, or single clock mii mode for receive or transmit. in addition, several additional bits are included to allow datapath selection for transmit and receive in multiport applications. table 9-19. rmii and bypass register (rbr), addresses 17h bit bit name default description 15 sim_write 0, rw simultaneous write: setting this bit in port a register space enables simultaneous write to phy registers in both ports. subsequent writes to port a registers will write to registers in both ports a and b. 1 = simultaneous writes to both ports. 0 = per-port write. 14 reserved 0, ro reserved: writes ignored, read as 0. 13 dis_tx_opt 0, rw disable rmii tx latency optimization: normally the rmii transmitter will minimize the transmit latency by realigning the transmit clock with the reference clock phase at the start of a packet transmission. setting this bit will disable phase realignment and ensure that idle bits will always be sent in multiples of the symbol size. this will result in a larger uncertainty in rmii transmit latency. 12:11 rx_port 00, rw receive port: see section 5.5 for more information on flexible port switching. 10:9 tx_source strap, rw transmit source: see section 5.5 for more information on flexible port switching. 00 = not strapped for extender mode. 10 = strapped for extender mode. 8 pmd_loop 0, rw pmd loopback: 0= normal operation. 1= remote (pmd) loopback. setting this bit will cause the device to loopback data received from the physical layer. the loopback is done prior to the mii or rmii interface. data received at the internal mii or rmii interface will be applied to the transmitter. this mode should only be used if rmii mode or single clock mii mode is enabled. 7 scmii_rx strap, rw single clock rx mii mode: 0= standard mii mode. 1= single clock rx mii mode. setting this bit will cause the device to generate receive data (rx_dv, rx_er, rxd[3:0]) synchronous to the x1 reference clock. rx_clk is not used in this mode. this mode uses the rmii elasticity buffer to tolerate variations in clock frequencies. this bit cannot be set if rmii_mode is set to a 1. this bit is strapped to 1 if extender_en is 1 and rmii mode is not strapped at hard reset. 6 scmii_tx strap, rw single clock tx mii mode: 0= standard mii mode. 1= single clock tx mii mode. setting this bit will cause the device to sample transmit data (tx_en, txd[3:0]) synchronous to the x1 reference clock. tx_clk is not used in this mode. this bit cannot be set if rmii_mode is set to a 1. this bit is strapped to 1 if extender_en is 1 and rmii mode is not strapped at hard reset. 5 rmii_mode strap, rw reduced mii mode: 0 = standard mii mode. 1 = reduced mii mode. 86 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 9-19. rmii and bypass register (rbr), addresses 17h (continued) bit bit name default description 4 rmii_rev1_0 0, rw reduced mii revision 1.0: 0 = (rmii revision 1.2) crs_dv will toggle at the end of a packet to indicate deassertion of crs. 1 = (rmii revision 1.0) crs_dv will remain asserted until final data is transferred. crs_dv will not toggle at the end of a packet. 3 rx_ovf_sts 0, ro/cor rx fifo over flow status: 0 = normal. 1 = overflow detected. 2 rx_unf_sts 0, ro/cor rx fifo under flow status: 0 = normal. 1 = underflow detected. 1:0 elast_buf[1:0] 01, rw receive elasticity buffer: this field controls the receive elasticity buffer which allows for frequency variation tolerance between the 50 mhz rmii clock and the recovered data. see section 5.2 for more information on elasticity buffer settings in rmii mode. see section 5.4 for more information on elasticity buffer settings in scmii mode. 9.2.5 led direct control register (ledcr) this register provides the ability to directly control any or all led outputs. it does not provide read access to leds. in addition, it provides control for the activity source and blinking led frequency. table 9-20. led direct control register (ledcr), address 18h bit bit name default description 15:9 reserved 0, ro reserved : writes ignored, read as 0. 8 ledact_rx 0, rw 1 = activity is only indicated for receive traffic 0 = activity is indicated for transmit or receive traffic 7:6 blink_freq 00, rw led blink frequency: these bits control the blink frequency of the led_link output when blinking on activity is enabled. 0 = 6hz 1 = 12hz 2 = 24hz 3 = 48hz 5 drv_spdled 0, rw 1 = drive value of spdled bit onto led_speed output 0 = normal operation 4 drv_lnkled 0, rw 1 = drive value of lnkled bit onto led_link output 0 = normal operation 3 drv_actled 0, rw 1 = drive value of actled bit onto led_act/led_col output 0 = normal operation 2 spdled 0, rw value to force on led_speed output 1 lnkled 0, rw value to force on led_link output 0 actled 0, rw value to force on led_act/led_col output copyright ? 2008 ? 2009, texas instruments incorporated register block 87 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.2.6 phy control register (phycr) this register provides control for phy functions such as mdix, bist, led configuration, and phy address. it also provides pause negotiation status. table 9-21. phy control register (phycr), address 19h bit bit name default description 15 mdix_en strap, rw auto-mdix enable: 1 = enable auto-neg auto-mdix capability. 0 = disable auto-neg auto-mdix capability. the auto-mdix algorithm requires that the auto-negotiation enable bit in the bmcr register to be set. if auto-negotiation is not enabled, auto-mdix should be disabled as well. 14 force_mdix 0, rw force mdix : 1 = force mdi pairs to cross. (receive on tptd pair, transmit on tprd pair) 0 = normal operation. 13 pause_rx 0, ro pause receive negotiated: indicates that pause receive should be enabled in the mac. based on anar[11:10] and anlpar[11:10] settings. this function shall be enabled according to ieee 802.3 annex 28b table 28b-3, ? pause resolution ? , only if the auto-negotiated highest common denominator is a full duplex technology. 12 pause_tx 0, ro pause transmit negotiated: indicates that pause transmit should be enabled in the mac. based on anar[11:10] and anlpar[11:10] settings. this function shall be enabled according to ieee 802.3 annex 28b table 28b-3, pause resolution, only if the auto-negotiated highest common denominator is a full duplex technology. 11 bist_fe 0, rw/sc bist force error: 1 = force bist error. 0 = normal operation. this bit forces a single error, and is self clearing. 10 psr_15 0, rw bist sequence select: 1 = psr15 selected. 0 = psr9 selected. 9 bist_status 0, ll/ro bist test status: 1 = bist pass. 0 = bist fail. latched, cleared when bist is stopped. for a count number of bist errors, see the bist error count in the cdctrl1 register. 8 bist_start 0, rw bist start: 1 = bist start. 0 = bist stop. 88 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 table 9-21. phy control register (phycr), address 19h (continued) bit bit name default description 7 bp_stretch 0, rw bypass led stretching: this will bypass the led stretching and the leds will reflect the internal value. 1 = bypass led stretching. 0 = normal operation. 6 led_cnfg[1] 0, rw led configuration 5 led_cnfg[0] strap, rw led_cnfg[1] led_cnfg[0] mode description don't care 1 mode 1 0 0 mode 2 1 0 mode 3 in mode 1 , leds are configured as follows: led_link = on for good link, off for no link led_speed = on in 100 mb/s, off in 10 mb/s led_act/led_col = on for activity, off for no activity in mode 2 , leds are configured as follows: led_link = on for good link, blink for activity led_speed = on in 100 mb/s, off in 10 mb/s led_act/led_col = on for collision, off for no collision full duplex, off for half duplex in mode 3 , leds are configured as follows: led_link = on for good link, blink for activity led_speed = on in 100 mb/s, off in 10 mb/s led_act/led_col = on for full duplex, off for half duplex 4:0 phyaddr[4:0] strap, rw phy address: phy address for port. copyright ? 2008 ? 2009, texas instruments incorporated register block 89 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.2.7 10 base-t status/control register (10btscr) this register is used for control and status for 10base-t device operation. table 9-22. 10base-t status/control register (10btscr), address 1ah bit bit name default description 15 10bt_serial strap, rw 10base-t serial mode (sni) 1 = enables 10base-t serial mode. 0 = normal operation. places 10 mb/s transmit and receive functions in serial network interface (sni) mode of operation. has no effect on 100 mb/s operation. 14:1 reserved 0, rw reserved: must be zero. 2 11:9 squelch 100, rw squelch configuration: used to set the squelch on threshold for the receiver. default squelch on is 330mv peak. 8 loopback_10_dis 0, rw 10base-t loopback disable: in half-duplex mode, default 10base-t operation loops transmit data to the receive data in addition to transmitting the data on the physical medium. this is for consistency with earlier 10base2 and 10base5 implementations which used a shared medium. setting this bit disables the loopback function. this bit does not affect loopback due to setting bmcr[14]. 7 lp_dis 0, rw normal link pulse disable: 1 = transmission of nlps is disabled. 0 = transmission of nlps is enabled. 6 force_link_10 0, rw force 10mb good link: 1 = forced good 10mb link. 0 = normal link status. 5 reserved 0, rw reserved: must be zero. 4 polarity ro/lh 10mb polarity status: this bit is a duplication of bit 12 in the physts register. both bits will be cleared upon a read of 10btscr register, but not upon a read of the physts register. 1 = inverted polarity detected. 0 = correct polarity detected. 3 reserved 0, rw reserved: must be zero. 2 reserved 1, rw reserved: must be set to one. 1 heartbeat_dis 0, rw heartbeat disable: this bit only has influence in half-duplex 10mb mode. 1 = heartbeat function disabled. 0 = heartbeat function enabled. when the device is operating at 100mb or configured for full duplex operation, this bit will be ignored - the heartbeat function is disabled. 0 jabber_dis 0, rw jabber disable: applicable only in 10base-t. 1 = jabber function disabled. 0 = jabber function enabled. 90 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.2.8 cd test and bist extensions register (cdctrl1) this register controls test modes for the 10base-t common driver. in addition it contains extended control and status for the packet bist function. table 9-23. cd test and bist extensions register (cdctrl1), address 1bh bit bit name default description 15:8 bist_error_count 0, ro bist error counter: counts number of errored data nibbles during packet bist. this value will reset when packet bist is restarted. the counter sticks when it reaches its max count. 7:6 reserved 0, rw reserved: must be zero. 5 bist_cont_mode 0, rw packet bist continuous mode: allows continuous pseudo random data transmission without any break in transmission. this can be used for transmit vod testing. this is used in conjunction with the bist controls in the phycr register (19h). for 10mb operation, jabber function must be disabled, bit 0 of the 10btscr (1ah), jabber_dis = 1. 4 cdpatten_10 0, rw cd pattern enable for 10mb: 1 = enabled. 0 = disabled. 3 reserved 0, rw reserved: must be zero. 2 10meg_patt_gap 0, rw defines gap between data or nlp test sequences: 1 = 15 s. 0 = 10 s. 1:0 cdpattsel[1:0] 00, rw cd pattern select[1:0]: if cdpatten_10 = 1: 00 = data, eop0 sequence. 01 = data, eop1 sequence. 10 = nlps. 11 = constant manchester 1s (10 mhz sine wave) for harmonic distortion testing. 9.2.9 phy control register 2 (phycr2) this register provides additional general control. table 9-24. phy control register 2 (phycr2), address 1ch bit bit name default description 15:1 reserved 0, ro reserved : writes ignored, read as 0. 0 9 soft_reset 0, rw/sc soft reset: resets the entire device minus the registers - all configuration is preserved. 1= reset, self-clearing. 8:0 reserved 0, ro reserved: writes ignored, read as 0. copyright ? 2008 ? 2009, texas instruments incorporated register block 91 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.2.10 energy detect control (edcr) this register provides control and status for the energy detect function. table 9-25. energy detect control (edcr), address 1dh bit bit name default description 15 ed_en strap, rw energy detect enable: allow energy detect mode. when energy detect is enabled and auto-negotiation is disabled via the bmcr register, auto-mdix should be disabled via the phycr register. 14 ed_auto_up 1, rw energy detect automatic power up: automatically begin power up sequence when energy detect data threshold value (edcr[3:0]) is reached. alternatively, device could be powered up manually using the ed_man bit (ecdr[12]). 13 ed_auto_down 1, rw energy detect automatic power down: automatically begin power down sequence when no energy is detected. alternatively, device could be powered down using the ed_man bit (edcr[12]). 12 ed_man 0, rw/sc energy detect manual power up/down: begin power up/down sequence when this bit is asserted. when set, the energy detect algorithm will initiate a change of energy detect state regardless of threshold (error or data) and timer values. in managed applications, this bit can be set after clearing the energy detect interrupt to control the timing of changing the power state. 11 ed_burst_dis 0, rw energy detect burst disable: disable bursting of energy detect data pulses. by default, energy detect (ed) transmits a burst of 4 ed data pulses each time the cd is powered up. when bursting is disabled, only a single ed data pulse will be send each time the cd is powered up. 10 ed_pwr_state 0, ro energy detect power state: indicates current energy detect power state. when set, energy detect is in the powered up state. when cleared, energy detect is in the powered down state. this bit is invalid when energy detect is not enabled. 9 ed_err_met 0, ro/cor energy detect error threshold met: no action is automatically taken upon receipt of error events. this bit is informational only and would be cleared on a read. 8 ed_data_met 0, ro/cor energy detect data threshold met: the number of data events that occurred met or surpassed the energy detect data threshold. this bit is cleared on a read. 7:4 ed_err_count 0001, rw energy detect error threshold: threshold to determine the number of energy detect error events that should cause the device to take action. intended to allow averaging of noise that may be on the line. counter will reset after approximately 2 seconds without any energy detect data events. 3:0 ed_data_count 0001, rw energy detect data threshold: threshold to determine the number of energy detect events that should cause the device to take actions. intended to allow averaging of noise that may be on the line. counter will reset after approximately 2 seconds without any energy detect data events. 92 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.3 link diagnostics registers - page 2 page 2 link diagnostics registers are accessible by setting bits [1:0] = 10 of pagesel (13h). 9.3.1 100mb length detect register (len100_det), page 2, address 14h this register contains linked cable length estimation in 100mb operation. the cable length is an estimation of the effective cable length based on the characteristics of the recovered signal. the cable length is valid only during 100mb operation with a valid link status indication. table 9-26. 100mb length detect register (len100_det), address 14h bit bit name default description 15:8 reserved 0, ro reserved: writes ignored, read as 0. 7:0 cable_len 0, ro cable length estimate: indicates an estimate of effective cable length in meters. a value of ff indicates cable length cannot be determined. 9.3.2 100mb frequency offset indication register (freq100), page 2, address 15h this register returns an indication of clock frequency offset relative to the link partner. two values can be read, the long term frequency offset, or a short term frequency control value. the frequency control value includes short term phase correction. the variance between the frequency control value and the frequency offset can be used as an indication of the amount of jitter in the system. table 9-27. 100mb frequency offset indication register (freq100), address 15h bit bit name default description 15 sample_freq 0, rw sample frequency offset: if sel_fc is set to a 0, then setting this bit to a 1 will poll the dsp for the long-term frequency offset value. the value will be available in the freq_offset bits of this register. if sel_fc is set to a 1, then setting this bit to a 1 will poll the dsp for the current frequency control value. the value will be available in the freq_offset bits of this register. this register bit will always read back as 0. 14:9 reserved 0, ro reserved: writes ignored, read as 0. 8 sel_fc 0, rw select frequency control: setting this bit to a 1 will select the current frequency control value instead of the frequency offset. this value contains frequency offset plus the short term phase correction and can be used to indicate amount of jitter in the system. the value will be available in the freq_offset bits of this register. 7:0 freq_offset 0, ro frequency offset: frequency offset value loaded from the dsp following assertion of the sample_freq control bit. the frequency offset or frequency control value is a twos-complement signed value in units of approximately 5.1562ppm. the range is as follows: 0x7f = +655ppm 0x00 = 0ppm 0x80 = -660ppm copyright ? 2008 ? 2009, texas instruments incorporated register block 93 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.3.3 tdr control register (tdr_ctrl), page 2, address 16h this register contains control for the time domain reflectometry (tdr) cable diagnostics. the tdr cable diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length and detect certain cabling faults. table 9-28. tdr control register (tdr_ctrl), address 16h bit bit name default description 15 tdr_enable 0, rw tdr enable: enable tdr mode. this forces powerup state to correct operating condition for sending and receiving tdr pulses. 14 tdr_100mb 0, rw tdr 100mb: sets tdr controller to use the 100mb transmitter. this allows for sending pulse widths in multiples of 8ns. pulses in 100mb mode will alternate between positive pulses and negative pulses. default operation uses the 10mb link pulse generator. pulses may include just the 50ns preemphasis portion of the pulse or the 100ns full link pulse (as controlled by setting tdr width). 13 tx_channel 0, rw transmit channel select: select transmit channel for sending pulses. pulse can be sent on the transmit or receive pair. 0 : transmit channel 1 : receive channel 12 rx_channel 0, rw receive channel select: select receive channel for detecting pulses. pulse can be monitored on the transmit or receive pair. 0 : transmit channel 1 : receive channel 11 send_tdr 0, rw/sc send tdr pulse: setting this bit will send a tdr pulse and enable the monitor circuit to capture the response. this bit will automatically clear when the capture is complete. 10:8 tdr_width 0, rw tdr pulse width: pulse width in clocks for the transmitted pulse. in 100mb mode, pulses are in 8ns increments. in 10mb mode, pulses are in 50ns increments, but only 50ns or 100ns pulses can be sent. sending a pulse of 0 width will not transmit a pulse, but allows for baseline testing. 7 tdr_min_mode 0, rw min/max mode control: this bit controls direction of the pulse to be detected. default looks for a positive peak. threshold and peak values will be interpreted appropriately based on this bit. 0 : max mode, detect positive peak 1 : min mode, detect negative peak 6 reserved 0, ro reserved : writes ignored, read as 0. 5:0 rx_threshold < 10_0000 > , rw rx threshold: this value provides a threshold for measurement to the start of a peak. if min mode is set to 0, data must be greater than this value to trigger a capture. if min mode is 1, data must be less than this value to trigger a capture. data ranges from 0x00 to 0x3f, with 0x20 as the midpoint. positive data is greater than 0x20, negative data is less than 0x20. 94 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.3.4 tdr window register (tdr_win), page 2, address 17h this register contains sample window control for the time domain reflectometry (tdr) cable diagnostics. the two values contained in this register specify the beginning and end times for the window to monitor the response to the transmitted pulse. time values are in 8ns increments. this provides a method to search for multiple responses and also to screen out the initial outgoing pulse. table 9-29. tdr window register (tdr_win), address 17h bit bit name default description 15:8 tdr_start 0, rw tdr start window: specifies start time for monitoring tdr response. 7:0 tdr_stop 0xff, rw tdr stop window: specifies stop time for monitoring tdr response. the stop window should be set to a value greater than or equal to the start window. 9.3.5 tdr peak register (tdr_peak), page 2, address 18h this register contains the results of the tdr peak detection. results are valid if the tdr_ctrl[11] is clear following sending the tdr pulse. table 9-30. tdr peak register (tdr_peak), address 18h bit bit name default description 15:14 reserved 0, ro reserved: writes ignored, read as 0. 13:8 tdr_peak 0, ro tdr peak value: this register contains the peak value measured during the tdr sample window. if min mode control (tdr_ctrl[7]) is 0, this contains the maximum detected value. if min mode control is 1, this contains the minimum detected value. 7:0 tdr_peak_time 0, ro tdr peak time: specifies the time for the first occurrence of the peak value. 9.3.6 tdr threshold register (tdr_thr), page 2, address 19h this register contains the results of the tdr threshold detection. results are valid if the tdr_ctrl[11] is clear following sending the tdr pulse. table 9-31. tdr threshold register (tdr_thr), address 19h bit bit name default description 15:9 reserved 0, ro reserved: writes ignored, read as 0. 8 tdr_thr_met 0, ro tdr threshold met: this bit indicates the tdr threshold was met during the sample window. a value of 0 indicates the threshold was not met. 7:0 tdr_thr_time 0, ro tdr threshold time: specifies the time for the first data that met the tdr threshold. this field is only valid if the threshold was met. copyright ? 2008 ? 2009, texas instruments incorporated register block 95 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.3.7 variance control register (var_ctrl), page 2, address 1ah the variance control and data registers provide control and status for the cable signal quality estimation function. the cable signal quality estimation allows a simple method of determining an approximate signal-to-noise ratio for the 100mb receiver. this register contains the programmable controls and status bits for the variance computation, which can be used to make a simple signal-to-noise ratio estimation. table 9-32. variance control register (var_ctrl), address 1ah bit bit name default description 15 var_rdy 0, ro variance data ready status: indicates new data is available in the variance data register. this bit will be automatically cleared after two consecutive reads ot var_data. 14:4 reserved 0, ro reserved: writes ignored, read as 0. 3 var_freeze 0, rw freeze variance registers: freeze var_data register. this bit is ensures that var_data register is frozen for software reads. this bit is automatically cleared after two consecutive reads of var_data. 2:1 var_timer 0, rw variance computation timer (in ms): selects the variance computation timer period. after a new value is written, computation is automatically restarted. new variance register values are loaded after the timer elapses. var_timer = 0 = > 2 ms timer (default) var_timer = 1 = > 4 ms timer var_timer = 2 = > 6 ms timer var_timer = 3 = > 8 ms timer time units are actually 2 17 cycles of an 8ns clock, or 1.048576ms. 0 var_enable 0, rw variance enable: enable variance computation. off by default. 9.3.8 variance data register (var_data), page 2, address 1bh this register contains the 32-bit variance sum. the contents of the data are valid only when var_rdy is asserted in the var_ctrl register. upon detection of var_rdy asserted, software should set the var_freeze bit in the var_ctrl register to prevent loading of a new value into the var_data register. since the variance data value is 32-bits, two reads of this register are required to get the full value. table 9-33. variance data register (var_data), address 1bh bit bit name default description 15:0 var_data 0, ro variance data: two reads are required to return the full 32-bit variance sum value. following setting the var_freeze control, the first read of this register will return the low 16 bits of the variance data. a second read will return the high 16 bits of variance data. 96 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
DP83849IF www.ti.com snosax8c ? june 2008 ? revised april 2009 9.3.9 link quality monitor register (lqmr), page 2, address 1dh this register contains the controls for the link quality monitor function. the link quality monitor provides a mechanism for programming a set of thresholds for dsp parameters. if the thresholds are violated, an interrupt will be asserted if enabled in the misr. monitor control and status are available in this register, while the lqdr register controls read/write access to threshold values and current parameter values. reading of lqmr register clears warning bits and re-arms the interrupt generation. in addition, this register provides a mechanims for allowing automatic reset of the 100mb link based on the link quality monitor status. table 9-34. link quality monitor register (lqmr), address 1dh bit bit name default description 15 lqm_enable 0, rw link quality monitor enable: enables the link quality monitor. the enable is qualified by having a valid 100mb link. in addition, the individual thresholds can be disabled by setting to the max or min values. 14:10 reserved 0, ro reserved: writes ignored, read as 0. 9 fc_hi_warn 0, ro/cor frequency control high warning: this bit indicates the frequency control high threshold was exceeded. this register bit will be cleared on read. 8 fc_lo_warn 0, ro/cor frequency control low warning: this bit indicates the frequency control low threshold was exceeded. this register bit will be cleared on read. 7 freq_hi_warn 0, ro/cor frequency offset high warning: this bit indicates the frequency offset high threshold was exceeded. this register bit will be cleared on read. 6 freq_lo_warn 0, ro/cor frequency offset low warning: this bit indicates the frequency offset low threshold was exceeded. this register bit will be cleared on read. 5 dblw_hi_warn 0, ro/cor dblw high warning: this bit indicates the dblw high threshold was exceeded. this register bit will be cleared on read. 4 dblw_lo_warn 0, ro/cor dblw low warning: this bit indicates the dblw low threshold was exceeded. this register bit will be cleared on read. 3 dagc_hi_warn 0, ro/cor dagc high warning: this bit indicates the dagc high threshold was exceeded. this register bit will be cleared on read. 2 dagc_lo_warn 0, ro/cor dagc low warning: this bit indicates the dagc low threshold was exceeded. this register bit will be cleared on read. 1 c1_hi_warn 0, ro/cor c1 high warning: this bit indicates the deq c1 high threshold was exceeded. this register bit will be cleared on read. 0 c1_lo_warn 0, ro/cor c1 low warning: this bit indicates the deq c1 low threshold was exceeded. this register bit will be cleared on read. copyright ? 2008 ? 2009, texas instruments incorporated register block 97 submit documentation feedback product folder links: DP83849IF
DP83849IF snosax8c ? june 2008 ? revised april 2009 www.ti.com 9.3.10 link quality data register (lqdr), page 2 this register provides read/write control of thresholds for the 100mb link quality monitor function. the register also provides a mechanism for reading current adapted parameter values. threshold values may not be written if the device is powered-down. table 9-35. link quality data register (lqdr), address 1eh bit bit name default description 15:14 reserved 0, ro reserved: writes ignored, read as 0. 13 sample_param 0, rw sample dsp parameter: setting this bit to a 1 enables reading of current parameter values and initiates sampling of the parameter value. the parameter to be read is selected by the lq_param_sel bits. 12 write_lq_thr 0, rw write link quality threshold: setting this bit will cause a write to the threshold register selected by lq_param_sel and lq_thr_sel. the data written is contained in lq_thr_data. this bit will always read back as 0. 11:9 lq_param_sel 0, rw link quality parameter select: this 3-bit field selects the link quality parameter. this field is used for sampling current parameter values as well as for reads/writes to threshold values. the following encodings are available: 000: deq_c1 001: dagc 010: dblw 011: frequency offset 100: frequency control 8 lq_thr_sel 0, rw link quality threshold select: this bit selects the link quality threshold to be read or written. a 0 selects the low threshold, while a 1 selects the high threshold. when combined with the lq_param_sel field, the following encodings are available {lq_param_sel, lq_thr_sel}: 000,0: deq_c1 low 000,1: deq_c1 high 001,0: dagc low 001,1: dagc high 010,0: dblw low 010,1: dblw high 011,0: frequency offset low 011,1: frequency offset high 100,0: frequency control low 100,1: frequency control high 7:0 lq_thr_data 0, rw link quality threshold data: the operation of this field is dependent on the value of the sample_param bit. if sample_param = 0: on a write, this value contains the data to be written to the selected link quality threshold register. on a read, this value contains the current data in the selected link quality threshold register. if sample_param = 1: on a read, this value contains the sampled parameter value. this value will remain unchanged until a new read sequence is started. 98 register block copyright ? 2008 ? 2009, texas instruments incorporated submit documentation feedback product folder links: DP83849IF
package option addendum www.ti.com 9-feb-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) op temp (c) top-side markings (4) samples DP83849IFvs/nopb active tqfp pfc 80 119 green (rohs & no sb/br) sn level-3-260c-168 hr -40 to 85 DP83849IFvs DP83849IFvsx/nopb active tqfp pfc 80 1000 green (rohs & no sb/br) sn level-3-260c-168 hr -40 to 85 DP83849IFvs (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) only one of markings shown within the brackets will appear on the physical device. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant DP83849IFvsx/nopb tqfp pfc 80 1000 330.0 24.4 15.0 15.0 1.45 20.0 24.0 q2 package materials information www.ti.com 21-dec-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) DP83849IFvsx/nopb tqfp pfc 80 1000 358.0 343.0 63.0 package materials information www.ti.com 21-dec-2012 pack materials-page 2
mechanical data mtqf009a october 1994 revised december 1996 post office box 655303 ? dallas, texas 75265 pfc (s-pqfp-g80) plastic quad flatpack 4073177 / b 11/96 40 21 0,13 nom 0,25 0,75 0,45 seating plane 0,05 min gage plane 0,27 41 0,17 20 60 1 61 80 sq sq 12,20 13,80 14,20 11,80 9,50 typ 1,05 1,20 max 0,95 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
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